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1 zarlink semiconductor inc. zarlink, zl and the zarlink semiconductor logo are trademarks of zarlink semiconductor inc. copyright 2003-2006, zarlink semiconductor inc. all rights reserved. features ? 12 10/100 mbps autosensing, fast ethernet ports with reduced mii interface ? single gigabit ethernet port ? supports both gmii and integrated physical coding sublayer with ten bit interface (tbi) logic to interface directly with gigabit transceivers ? two-chip solution for 24+2 configuration - 32-bit wide bi-directional pipe at 100 mhz pro- vides 6.4 gbps pipe to connect two mds213 chips ? supports up to 6.548 mpps system throughput using non-blocking architecture ? high performance layer 2 packet forwarding and filtering at full wire speed. ? very low latency through single store and forward at ingress port and cut-through switching at destination ports ? port trunking and load sharing for high bandwidth links between switches ? on-chip address lookup engine and memory for up to 2 k mac addresses ? parallel flash interface for fast self initialization ? supports packet filtering and port security - system wide filtering - static mac destination and source address filtering - vlan for multicast/broadcast filtering - protocol filtering - local port filtering - aging control for secure mac addresses - provides 256-port and id tagged virtual lans (vlans) 802.1q ? id tagging insertion/extraction ? supports ip multicasting through igmp snooping ? xpressflow quality of service (qos), ieee 802.1p, supports 4 level transmission priorities, weighted fair queuing based packet scheduling, user mapping of priority levels and weights ? full duplex ethernet ieee 803.2x flow control minimizes traffic congestion ? supports back-pressure flow control for half duplex mode ? flooding and broadcasting control ? link status and tx/rx activity through serial led interface april 2006 ordering information mds213cg 456 pin hsbga trays MDS213CG2 456 pin hsbga** trays **pb free tin/silver/copper 0 c to 70 c mds213 12-port 10/100mbps + 1gbps ethernet switch data sheet figure 1 - 24 10/100mbps + 2gbp s port system configuration mds213 mds213 sram sram sram cpu flash 4 x 10/100 fast ethernet 4 x 10/100 fast ethernet 4 x 10/100 fast ethernet 4 x 10/100 fast ethernet 4 x 10/100 fast ethernet 4 x 10/100 fast ethernet 1g 1g g ethernet g ethernet cpu bus xpipe 32 bit 64 bit 64 bit 24 + 2 system configuration
mds213 data sheet 2 zarlink semiconductor inc. ? up to 64 k using management cpu memory ? up to 16 k using external buffer memory ? standard software modules available: ? browser, gui, and text menu ? ieee 802.1d spanning tree algorithm - snmp management - telnet for remote control console - automatic booting via tftp protocols. - remote monitoring (rmon) and storage for a management agent ? igmp for ip multicast ?gvrp, gmrp ? packaged in 456-pin ball grid array description the zarlink mds213 is a 12-port 10/100 mbps + 1 gbps hi gh-performance, non-blocking ethernet switch with on- chip address memory and address lookup engine. a single chip provides 12 - 10/100 mbps ports and 1 - 1000 mbps port. the mds213 can be utilized in both managed and unmanaged switching applications. the 3.2 gbps xpipe allows a high-speed connection betwe en two mds213 chips, providing a optimal, low-cost, workgroup switch with 24 10/100 fast ethe rnet ports and 2 gigabit ethernet ports. in half-duplex mode, all ports support back pressure flow co ntrol to minimize the risk of losing data for long activity bursts. in full-duplex mode, ieee 802.3x frame based flow c ontrol is used. with full-duplex capabilities, each fast ethernet ports supports 200 mbps aggr egate bandwidth connections, while t he gigabit ethernet port supports 2 gbps to desktops, servers, or other high-performance switches. the physic al coding sublayer is integrated on- chip with ten bit interface (tbi) and this physical codi ng sublayer can be bypassed when the gmii interface is used. the mds213 supports port trunking/load sharing on the 10 /100 mbps ports. port trunking/load sharing can be used to group ports between interlinked switches for increased system bandwidth. ports within a trunk must reside within a single mds213, such that trunks may not be configured across two switches. the on-chip address lookup engine supports up to 2 k mac addresses and up to 256 ieee 802.1q virtual lans (vlan). each port may be programmed to rec ognize vlans, and will transmit fram es along with their vlan tags, for interoperability, to system s that support vlan tagging. each port independently collects statistical informat ion using snmp and the remote monitoring management information base (rmon - mib). access to these statisti cal counter/registers are prov ided via the cpu interface. snmp management frames may be received and/or transmi tted via the cpu interface and thus creates a complete network management solution. the mds213 utilizes cost ef fective, high performance, pipelined sbram to achieve full wire speed on all ports simultaneously. data is buffered into memory, using 0-128 by te bursts, from the ingress ports, and transferred to an internal transmit fifo, before being sent from the fr ame memory to the egress output ports. extremely high memory bandwidth is therefore achieved, which allows eac h of the ports to be active without creating a memory bottleneck. the mds213 is fabricated with 2.5 v technology, where the inputs are 3.3 v tolerant and the outputs are capable of directly interfacing to low-voltage ttl levels. the za rlink mds213 is packaged in a 456-pin ball grid array.
mds213 data sheet 3 zarlink semiconductor inc. figure 2 - system block diagram note: all registers ar e 32-bit width. the control bus is 32-bits wide and the memory bus is 64-bits wide. the mds213 contains 12 fast ethernet ports. the led interface has 3 output signals (1 data and 2 control). the xpipe is 32-bits wide. switch cpu interface control memory 2k sram frame memory interface frame buffer memory 64 search engine frame engine reduced xpipe engine sbram twelve 10/100 macs gmac gmii/pcs(tbi) interface led xface hisc tm registers 32 3.2gbps xpipe tm gmii or pcs rmii 32 32
mds213 data sheet table of contents 4 zarlink semiconductor inc. 1.0 ball signal descriptions and assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 1.1 ball signal assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.0 ball-signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.0 the media access control (mac) and gigabit (gmac). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 3.1 mac/gmac configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 3.2 the inter-frame gap . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 3.3 ethernet frame limits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 3.4 collision handling and avoidance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 3.5 auto-negotiation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 3.6 vlan support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 3.7 mac control frames. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 3.8 flow control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 3.8.1 collision-based flow control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 3.8.2 ieee 802.3x flow control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 3.9 frame bursting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 4.0 frame engine description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 4.1 transmission scheduling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 4.2 buffer management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 5.0 frame buffer memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 5.1 frame buffer memory configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 5.2 frame buffer memory usage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 5.2.1 memory allocation of a managed system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 5.2.2 frame data buffers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 5.2.3 transmission queues . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 5.2.4 mailing list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 5.2.5 vlan table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 5.2.6 vlan mac association table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 5.2.7 unmanaged system memory allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 5.3 the frame memory interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 5.3.1 local memory interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 6.0 search engine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 6.1 layer 2 search process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 6.1.1 vlan unaware . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 6.1.2 vlan aware. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 6.2 address and vlan learning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 6.3 flooding and packet control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 6.4 packet filtering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 6.5 address aging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 6.6 ip multicast . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 7.0 the high density instruction set computer (hisc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 7.1 description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 7.2 hisc architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 7.3 hisc operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 7.3.1 resource initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 7.3.2 resource management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 7.3.3 switching database management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 7.3.4 send and receive frames for management cpu. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 7.3.5 communication between hisc and switching hardware . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 7.3.6 communication between search engine and hisc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 7.3.7 communication between hisc and frame engine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 7.4 communication between management cpu and hisc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
mds213 data sheet table of contents 5 zarlink semiconductor inc. 7.4.1 cpu-hisc communication using queues . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 7.4.2 mailbox. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 7.4.3 cpu-hisc mail . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 7.4.4 hisc-cpu mail . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 8.0 the xpipe . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 8.1 xpipe connection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 8.2 xpipe timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 9.0 physical layer (phy) interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 9.1 reduced mii (rmii) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 9.2 the gigabit media independent interface (gmii) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 9.2.1 the mii management interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 9.2.2 mii command and status registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 9.3 the physical coding sublayer with ten bit interface (tbi): . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 10.0 the control bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 10.1 external cpu support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 10.1.1 power on/reset configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 10.1.2 cpu bus clock interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 10.1.3 address and data buses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 10.1.4 bus master . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 10.1.5 input/output mapped interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 10.1.6 interrupt request . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 10.2 control bus cycle waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 10.3 the cpu interface in unmanaged mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 10.3.1 arbiter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 10.4 cpu interface in managed mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 10.4.1 cpu access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 11.0 the led interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 11.1 led interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 11.1.1 function description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 11.1.2 port status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 11.1.3 led interface time diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 12.0 data forwarding protocol and data flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 12.1 data forwarding protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 12.1.1 frame reception . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 12.1.2 unicast frame forwarding. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 12.1.3 multicast frame forwarding. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 12.2 flow for data frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 12.2.1 unicast data frame to lo cal device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 12.2.2 unicast data frame to remote devi ce . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 12.2.3 multicast data frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 12.3 flow for cpu control frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 12.3.1 cpu transmitting unicast cpu frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 12.3.2 cpu transmitting multicast cpu frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 12.3.3 cpu receiving unicast frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 12.3.4 cpu receiving multicast frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 13.0 port mirroring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 13.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 13.2 physical pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 13.2.1 setting register for port mirroring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 13.2.1.1 apmr- port mirroring register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 14.0 virtual local area networks (vlan) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
mds213 data sheet table of contents 6 zarlink semiconductor inc. 14.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 14.2 vlan implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 14.2.1 static definitions of vlan membership . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 14.2.2 dynamic learning of vlan membership . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54 14.2.3 dynamic learning of remote vlan . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 14.2.4 mds213 data structures for vlan implementation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 14.2.4.1 vlan id table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 14.2.4.2 vlan mac table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 14.2.4.3 vlan port mapping table (vmap) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 14.2.4.4 port vlan id (pvid) register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 15.0 ip multicast . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 15.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 15.2 igmp and ip multicast filtering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 15.3 implementation in mds213 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 15.3.1 mct table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 15.3.1.1 mct structure for unicast frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 15.3.2 mct structure for ip multicast packet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 16.0 quality of service (qos) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 16.1 weighted round robin transmission strategy. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 16.2 buffer management functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 17.0 port trunking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 17.1 unicast packet forwarding. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 17.2 multicast packet forwarding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 17.2.1 select one forwarding port per trunk group . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62 17.2.2 blocking multicast packets back to the source trunk . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 17.3 mac address assignment. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 18.0 register definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 18.1 register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 18.2 register definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 18.2.1 device configuration register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 18.2.1.1 gcr - global control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 18.2.1.2 dcr0 - device status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 18.2.1.3 dcr1 - signature, revision & id register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 18.2.1.4 dcr2 - device configurat ion register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 9 18.2.1.5 dcr3 - interfaces status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72 18.2.1.6 memp - memory packed register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 18.2.2 interrupt control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 18.2.3 buffer memory interface register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 18.2.3.1 mwars - memory write address re gister - single cycle . . . . . . . . . . . . . . . . . . . . . . . . . 74 18.2.3.2 mrars - memory read address re gister - single cycle . . . . . . . . . . . . . . . . . . . . . . . . . . 74 18.2.3.3 address registers for burst cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75 18.2.3.4 memory read/write data registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 6 18.2.3.5 vtbp - vlan id table base pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 18.2.3.6 mbcr - multicast buffer control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 18.2.3.7 ama - ram counter block access register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 18.2.3.8 reserve register 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 18.2.3.9 reserve register 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 18.2.4 frame control buffers management register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 18.2.4.1 fcbsl - fcb queue . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 18.2.4.2 fcbst - fcb queue - buffer low threshold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 18.2.4.3 bct - (fcb) buffer counter threshold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 18.2.4.4 bchl - buffer counter hi-low selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 9
mds213 data sheet table of contents 7 zarlink semiconductor inc. 18.2.5 queue management register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 18.2.5.1 cinq - cpu input queue . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 18.2.5.2 cotq - cpu output queue. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80 18.2.6 switching control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 18.2.6.1 hpcr - hisc processor control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 18.2.6.2 hmcl0 - hisc micro-code loading port - low . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 18.2.6.3 hmcl1 - hisc micro-code loading port - high. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 18.2.6.4 ms0r micro sequence 0 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 1 18.2.6.5 ms0r micro sequence 1 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 1 18.2.6.6 flooding control register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 18.2.6.7 mcat - mct aging timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 18.2.6.8 tpmxr ? trunk port mapping table index register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 18.2.6.9 tpmtd - trunking port mapping t able data register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 18.2.6.10 ptr - pacing time regulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .83 18.2.6.11 mtcr - mct threshold & counter register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 18.2.7 link list management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 18.2.7.1 lks - link list status register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 18.2.7.2 ambx - mail box access port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 18.2.7.3 afml - free mail box list access port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 5 18.2.8 access control function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 18.2.8.1 avtc - vlan type code register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 18.2.8.2 axsc - transmission scheduling control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 18.2.8.3 attl - transmission timing control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 18.2.9 mii serial management channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 18.2.9.1 amiic - mii command register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .86 18.2.9.2 amiis - mii status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 18.2.10 flow control management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 18.2.10.1 afcria - flow control ram input address. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 18.2.10.2 afcrid0 - flow control ram input data 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 18.2.10.3 afcrid1 - flow control ram input data 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 18.2.10.4 afcr - flow control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 18.2.10.5 amar[1:0] - multicast address reg. for mac cont rol frames. . . . . . . . . . . . . . . . . . . . . 89 18.2.10.6 amct - mac control frame type code register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 18.2.10.7 adar [1:0] - base mac address registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 18.2.10.8 adaor0 - mac offset address register 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 18.2.10.9 adaor1 - mac offset address register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 18.2.10.10 acktm - timer for sof checking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 18.2.10.11 afcht10 - flow control hold ti me of 10mbps port . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 18.2.10.12 afcht 100 - flow control hold time of 100mbps port . . . . . . . . . . . . . . . . . . . . . . . . . 91 18.2.10.13 afcht1000 - flow control hold time of giga port. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 18.2.10.14 afcoft10 - flow control off time of 10mbps prot . . . . . . . . . . . . . . . . . . . . . . . . . . 92 18.2.10.15 afcoft100 - flow c ontrol off time of 100mbps port . . . . . . . . . . . . . . . . . . . . . . . . 92 18.2.10.16 afcoft1000 - flow control off time of giga port. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 18.2.11 access control function group 2 (chip level) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .93 18.2.11.1 apmr- port mirroring register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 18.2.11.2 pfr - protocol filtering register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 18.2.11.3 thkm [0:7] - trunking forwarding port mask 0-7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 18.2.11.4 ipmcas - ip multicast mac address signature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 18.2.11.5 ipmcmsk- ip multicast mac address mask . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 18.2.11.6 cfcbhdl - fcb handle register for cpu read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 18.2.11.7 cpu access internal rams (tables) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 18.2.11.8 cpuircmd - cpu internal ram command register . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
mds213 data sheet table of contents 8 zarlink semiconductor inc. 18.2.11.9 cpuirdat - cpu internal ram data register. . . . . . . . . . . . . . . . . . . . . . . . . . . 98 18.2.11.10 cpuirrdy - internal ram read ready for cpu . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 18.2.11.11 ledr- led register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 18.2.12 ethernet mac port control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 18.2.12.1 ecr0 - ecr0 - mac port control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 18.2.12.2 ecr1 - mac port configuration register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 18.2.12.3 ecr2 - mac port interrupt mask register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 18.2.12.4 ecr3 - mac port interrupt status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 18.2.12.5 ecr4 - port status counter wrapped signal. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 18.2.12.6 pvid register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 19.0 dc electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 19.1 absolute maximum ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 19.2 dc electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 20.0 ac specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 20.1 xpipe interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 20.2 cpu bus interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 20.3 local sbram memory interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
mds213 data sheet list of figures 9 zarlink semiconductor inc. figure 1 - 24 10/100mbps + 2gbps port system configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 figure 2 - system block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 figure 3 - frame with carrier extension and frame bursting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 figure 4 - frame buffer memory configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 figure 5 - memory map of managed system. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 figure 6 - memory map of an unmanaged system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 figure 7 - typical packet header information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 figure 8 - xpipe system block diagram for the mds213 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 figure 9 - xpipe message header. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 figure 10 - basic timing diagram of xpipe . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 figure 11 - cpu interface configuration in managed mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 figure 12 - control bus configuration in unmanaged mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 figure 13 - control bus i/o . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 figure 14 - block diagram of the arbiter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 figure 15 - little and big endian byte swapping operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 figure 16 - an example of byte swapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 figure 17 - led interface connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 figure 18 - time diagram of led interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 figure 19 - configuration of mirror port for mds213 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 figure 20 - data structure diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 figure 21 - vlan id table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 figure 22 - vlan mac table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 figure 23 - port mapping table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 figure 24 - forwarding port mask table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 figure 25 - multicast packet forwarding example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 figure 26 - xpipe interface - output valid delay timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 figure 27 - ac characteristics - cpu bus interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 figure 28 - local memory interface - input setup and output va lid delay timing . . . . . . . . . . . . . . . . . . . . . . . 11 3 figure 29 - port mirroring interface - input setup and hold timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 figure 30 - port mirroring interface - output delay timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 figure 31 - reduce media independent interface - input setup and hold timing. . . . . . . . . . . . . . . . . . . . . . . . 114 figure 32 - reduce media independent interface - output delay timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 figure 33 - input setup and hold timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 figure 34 - output valid delay timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 figure 35 - led interface - output delay timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
mds213 data sheet list of tables 10 zarlink semiconductor inc. table 1 - type and size of memory chips . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 table 2 - frame buffer memory usage for managed mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 table 3 - frame buffer memory usage for unmanaged mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 table 4 - summary description of the source and target end signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 table 5 - rmii specification signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 table 6 - bootstrapping options. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 table 7 - led signal names and descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 table 8 - mds213 register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 table 9 - global control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 table 10 - device status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 table 11 - ac characteristics - xpipe interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 table 12 - ac characteristics - cpu bus interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 table 13 - ac characteristics - local sbram memory interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 table 14 - ac characteristics - port mirroring interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 table 15 - ac characteristics - reduced media independent interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 table 16 - ac characteristics - gigabit media independent interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 table 17 - ac characteristics - physical media attachment interf ace . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 table 18 - ac characteristics - led interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
mds213 data sheet 11 zarlink semiconductor inc. 1.0 ball signal descriptions and assignments vcc = 3.3vdc for i/o (16 balls) vdd = 2.5vdc for core logic (10 balls) gnd = digital ground for bo th vcc and vdd (42 balls) avdd = 2.5vdc for analog pll (1 ball) agnd = isolated analog ground for avdd (1 ball) nc = no connection reserved = do not connect 1 2345 67891011121314151617181920212223242526 aagndl_a2 0 l_a1 9 l_a1 1 l_a8 l_a4 x_d o29 x_d o25 x_d o20 x_d o16 x_d o13 x_d o8 x_d o5 x_d o2 x_dc lko x_di 29 x_di 25 x_di 21 x_di 17 x_di 12 x_di 8 x_di 4 x_di 2 p_cs i# p_re q1 p_gn tc b reser ved rese rved l_a1 8 l_a1 4 l_a1 0 l_a5 x_d o30 x_d o26 x_d o21 x_d o18 x_d o14 x_d o10 x_d o4 x_d o3 x_fc o x_di 28 x_di 23 x_di 20 x_di 16 x_di 11 x_di 7 x_di 3 x_dc lki rese rved nc nc cavddrese rved rese rved l_a1 7 l_a1 3 l_a6 x_d o31 x_d o28 x_d o24 x_d o19 x_d o15 x_d o12 x_d o6 x_d o1 x_di 31 x_di 27 x_di 22 x_di 18 x_di 14 x_di 10 x_di 6 x_dn i rese rved p_re qc p_br dy p_bl ast d l_d4 l_d1 l_cl k nc l_a1 6 l_a1 2 l_a7 l_a3 x_d o27 x_d o23 x_d o17 x_d o11 x_d o7 x_de no x_di 30 x_di 24 x_di 19 x_di 15 x_di 9 x_di 5 x_di 1 x_fc i p_in t p_rd y# p_rs t# p_a8 e l_d6 l_d5 l_d2 l_d0 gnd l_a1 5 vcc l_a9 vdd _x_d o22 vcc x_d o9 gnd x_d o0 x_di 26 vcc x_di 13 vdd x_di 0 vcc p_g nt1 gnd p_ad s# p_a1 0 p_cl k p_a7 f l_d11 l_d1 0 l_d8 l_d3 t_m ode # p_r wc# p_a9 p_a4 p_a3 p_a2 g l_d1 5 l_d1 4 l_d1 3 l_d7 vcc vcc p_a6 p_d3 1 p_d3 0 p_d2 9 h l_d2 0 l_d1 8 l_d1 6 l_d1 2 l_d9 p_a5 p_a1 p_d2 8 p_d2 6 p_d2 4 j l_d2 4 l_d2 3 l_d2 1 l_d1 7 vdd vdd p_d2 7 p_d2 3 p_d2 1 p_d2 0 k l_d2 9 l_d2 7 l_d2 6 l_d2 2 l_d1 9 p_d2 5 p_d2 2 p_d1 9 p_d1 8 p_d1 6 l l_we o# l_d3 1 l_d3 0 l_d2 8 vcc gnd gnd gnd gnd gnd gnd vcc p_d1 7 p_d1 4 p_d1 3 p_d1 2 m l_bw 0# l_oe 0# l_w e1# l_oe 1# l_d2 5 gnd gnd gnd gnd gnd gnd p_d1 5 p_d1 0 p_d1 1 p_d9 p_d8 n l_bw 3# l_ad s# l_b w2# l_b w1# s_cl k gnd gnd gnd gnd gnd gnd vdd p_d7 p_d6 p_d4 p_d5 p l_bw 5 l_b w4 l_b w7 l_b w6 vdd gnd gnd gnd gnd gnd gnd p_d0 t_d0 p_d1 p_d3 p_d2 r l_d3 3 l_d3 4 l_d3 6 l_d3 5 l_d3 2 gnd gnd gnd gnd gnd gnd t_d1 0 t_d4 t_d3 t_d2 t_d1 t l_d3 7 l_d3 8 l_d3 9 l_d4 1 vcc gnd gnd gnd gnd gnd gnd vcc t_d9 t_d7 t_d6 t_d5 u l_d4 0 l_d4 2 l_d4 3 l_d4 6 l_d4 7 t_d2 0 t_d1 5 t_d1 2 t_d1 1 t_d8 v l_d4 4 l_d4 5 l_d4 8 l_d5 1 vdd vdd t_d1 9 t_d1 6 t_d1 4 t_d1 3 w l_d4 9 l_d5 0 l_d5 2 l_d5 6 l_d5 7 pm_ do[1] t_d2 5 t_d2 1 t_d1 8 t_d1 7 y l_d5 3 l_d5 4 l_d5 5 l_d6 1 vcc vcc pm_ den o t_d2 4 t_d2 3 t_d2 2 aa l_d5 8 l_d5 9 l_d6 0 m_cl ki m0_t xd0 m12_ rxd5 le_# syn ci pm_ di[1] pm_ di[0] pm_ deni ab l_d6 2 l_d6 3 m0_t xen m0_c rs_d v gnd m2_l nk vcc m3_ crs _dv vdd m5_l nk vcc m6_t xd1 m8_t xd0 gnd m9_t xd1 vcc m10_ rxd1 vdd m11_ txd0 vcc m12_ txer gnd m_m dc le_# clk o le_s ync o pm_ do[0] ac m0_l nk m0_t xd1 m0_r xd1 m1_t xen m2_t xd1 m2_ rxd 1 m3_t xd1 m4_l nk m4_ rxd 1 m5_t xd0 m6_t xen m7_l nk m7_c rs_d v m8_r xd1 m9_t xen m10_ txen m10_ rxd0 m11_ rxd1 m12_ txd0 m12_ txd3 m12_ txd6 m12_ rxe r m12_ rxd4 m_m dio le_d i le_d o ad nc m0_r xd0 m1_t xd1 m2_t xen m2_c rs_d v m3_t xd0 m4_t xen m4_ crs _dv m5_t xd1 m5_ rxd 0 m6_c rs_d v m7_t xen m7_r xd1 m8_c rs_d v m9_t xd0 m9_r xd0 m10_ txd0 m11- txen m11_ rxd0 m12_ lnk m12_ txd2 m12_ txd7 m12_ rxd v m12_ rxd3 m12_ rxcl k m12_ rxd0 ae nc m1_l nk m1_r xd0 m2_t xd0 m3_l nk m3_ rxd 1 m4_t xd1 m4_ rxd 0 m5_ crs _dv m6_l nk m6_r xd1 m7_t xd1 m8_l nk m8_t xen m9_l nk m9_r xd1 m10_ txd1 m11_ lnk m11_ crs_ dv m12_ txcl k m12_ txd1 m12_ txd5 m12_ txen m12_ rxd7 nc m12_ rxd1 af m1_t xd0 m1_c rs_ dv m1_r xd1 m2_r xd0 m3_t xen m3_ rxd 0 m4_t xd0 m5_t xen m5_ rxd 1 m6_t xd0 m6_r xd0 m7_t xd0 m7_r xd0 m8_t xd1 m8_r xd0 m9_c rs_ dv m10_ lnk m10_ crs_ dv m11_ txd1 m12_ crs m12_ col m12_ txd4 gref _clk m12_ rxd6 nc m12_ rxd2 1 2345 67891011121314151617181920212223242526
mds213 data sheet 12 zarlink semiconductor inc. 1.1 ball signal assignments signal name ball no. nc d4 reserved c3 agnd a1 reserved b1 avdd c1 t_mode# f5 reserved c2 l_clk d3 l_d0 e4 l_d1 d2 l_d2 e3 l_d3 f4 l_d4 d1 l_d5 e2 l_d6 e1 l_d7 g4 l_d8 f3 l_d9 h5 l_d10 f2 l_d11 f1 l_d12 h4 l_d13 g3 l_d14 g2 l_d15 g1 l_d16 h3 l_d17 j4 l_d18 h2 l_d19 k5 l_d20 h1 l_d21 j3 l_d22 k4 l_d23 j2 l_d24 j1 l_d25 m5 l_d27 k2 l_d26 k3 l_d28 l4 l_d29 k1 l_d30 l3 l_d31 l2 l_we0# l1 l_oew# m2 l_we1# m3 l_oe1# m4 l_bw0# m1 l_bw1# n4 s_clk n5 l_bw2# n3 l_bw3# n1 l_ads# n2 l_bw4# p2 l_bw5# p1 l_bw6# p4 l_bw7# p3 l_d32 r5 l_d33 r1 l_d34 r2 l_d35 r4 l_d36 r3 l_d37 t1 l_d38 t2 l_d39 t3 l_d40 u1 l_d41 t4 l_d42 u2 l_d43 u3 signal name ball no. l_d44 v1 l_d45 v2 l_d46 u4 l_d47 u5 l_d48 v3 l_d49 w1 l_d50 w2 l_d51 v4 l_d52 w3 l_d53 y1 l_d54 y2 l_d55 y3 l_d56 w4 l_d57 w5 l_d58 aa1 l_d59 aa2 l_d60 aa3 l_d61 y4 l_d62 ab1 l_d63 ab2 m0_lnk ac1 m_clki aa4 m0_txen ab3 m0_txd1 ac2 m0_txd0 aa5 m0_crs_dv ab4 m0_rxd1 ac3 m0_rxd0 ad2 nc ad1 nc ae1 m1_lnk ae2 m1_txen ac4 m1_txd1 ad3 m1_txd0 af1 signal name ball no.
mds213 data sheet 13 zarlink semiconductor inc. m1_crs_dv af2 m1_rxd1 af3 m1_rxd0 ae3 m2_lnk ab6 m2_txen ad4 m2_txd1 ac5 m2_txd0 ae4 m2_crs_dv ad5 m2_rxd1 ac6 m2_rxd0 af4 m3_lnk ae5 m3_txen af5 m3_txd1 ac7 m3_txd0 ad6 m3_crs_dv ab8 m3_rxd1 ae6 m3_rxd0 af6 m4_lnk ac8 m4_txen ad7 m4_txd0 ae7 m4_txd0 af7 m4_crs_dv ad8 m4_rxd1 ac9 m4_rxd0 ae8 m5_lnk ab10 m5_txen af8 m5_txd1 ad9 m5_txd0 ac10 m5_crs_dv ae9 m5_rxd1 af9 m5_rxd0 ad10 m6_lnk ae10 m6_txen ac11 m6_txd1 ab12 signal name ball no. m6_txd0 af10 m6_crs_dv ad11 m6_rxd1 ae11 m6_rxd0 af11 m7_lnk ac12 m7_txen ad12 m7_txd1 ae12 m7_txd0 af12 m7_crs_dv ac13 m7_rxd1 ad13 m7_rxd0 af13 m8_lnk ae13 m8_txen ae14 m8_txd1 af14 m8_txd0 ab13 m8_crs_dv ad14 m8_rxd1 ac14 m8_rxd0 af15 m9_lnk ae15 m9_txen ac15 m9_txd1 ab15 m9_txd0 ad15 m9_crs_dv af16 m9_rxd1 ae16 m9_rxd0 ad16 m10_lnk af17 m10_txen ac16 m10_txd1 ae17 m10_txd0 ad17 m10_crs_dv af18 m10_rxd1 ab17 m10_rxd0 ac17 m11_lnk ae18 m11_txen ad18 signal name ball no. m11_txd1 af19 m11_txd0 ab19 m11_crs_dv ae19 m11_rxd1 ac18 m11_rxd0 ad19 m12_crs af20 m12_txclk/gp_txcl k ae20 m12_lnk/gp_lnk ad20 m12_txd0/gp_txd9 ac19 m12_col/gp_rxclk1 af21 m12_txd1/gp_txd8 ae21 m12_txd2/gp_txd7 ad21 m12_txd3/gp_txd6 ac20 m12_txd4/gp_txd5 af22 m12_txd5/gp_txd4 ae22 gref_clk af23 m12_txd6/gp_txd3 ac21 m12_txd7/gp_txd2 ad22 m12_tx_en/gp_txd1 ae23 m12_tx_er/gp_txd0 ab21 m12_rx_er/gp_rxd0 ac22 m12_rx_dv/gp_rxd1 ad23 m12_rxd7/gp_rxd2 ae24 m12_rxd6/gp_rxd3 af24 nc af25 nc ae25 m12_rxd5/gp_rxd4 aa22 m12_rxd4/gp_rxd5 ac23 m12_rxd3/gp_rxd6 ad24 m12_rxd2/gp_rxd7 af26 m12_rxd1/gp_rxd8 ae26 m12_rxd0/gp_rxd9 ad26 m12_rxclk/gp_ rsclk0 ad25 signal name ball no.
mds213 data sheet 14 zarlink semiconductor inc. m_mdio ac24 m_mdc ab23 le_di ac25 le_clko ab24 le_synci aa23 le_do ac26 le_synco ab25 t_d31/pm_do[1] w22 t_d30/pm_do[0] ab26 t_d29/pm_deno y23 t_d28/pm_di[1] aa24 t_d27/pm_di[0] aa25 t_d26/pm_deni aa26 t_d25 w23 t_d24 y24 t_d23 y25 t_d22 y26 t_d21 w24 t_d20 u22 t_d19 v23 t_d18 w25 t_d17 w26 t_d16 v24 t_d15 u23 t_d14 v25 t_d13 v26 t_d12 u24 t_d11 u25 t_d10 r22 t_d9 t23 t_d9 t23 t_d8 u26 t_d7 t24 t_d6 t25 signal name ball no. t_d5 t26 t_d4/bs_rdyop r23 t_d3/bs_psd r24 t_d2/bs_swm r25 t_d1/bs_rw r26 t_d0/bs_bmod p23 t_d0 p22 p_d1 p24 p_d2 p26 p_d3 p25 p_d4 n25 p_d5 n26 p_d6 n24 p_d7 n23 p_d8 m26 p_d9 m25 p_d10 m23 p_d11 m24 p_d12 l26 p_d13 l25 p_d14 l24 p_d15 m22 p_d16 k26 p_d17 l23 p_d18 k25 p_d19 k24 p_d20 j26 p_d21 j25 p_d22 k23 p_d23 j24 p_d24 h26 p_d25 k22 p_d26 h25 p_d27 j23 signal name ball no. p_d28 h24 p_d29 g26 p_d30 g25 p_d31 g24 p_a1 h23 p_a2 f26 p_a3 f25 p_a4 f24 p_a5 h22 p_a6 g23 p_a7 e26 p_clk e25 p_a8 d26 p_a9 f23 p_a10 e24 p_rst# d25 p_rwc# f22 p_ads# e23 p_rdy# d24 p_brdy# c25 p_blast# c26 nc b26 nc b25 p_int d23 p_reqc c24 p_gntc a26 p_req1 a25 p_gnt1 e21 p_csi# a24 reserved b24 reserved c23 x_fci d22 x_dclki b23 x_dni c22 signal name ball no.
mds213 data sheet 15 zarlink semiconductor inc. x_di0 e19 x_di1 d21 x_di2 a23 x_di3 b22 x_di4 a22 x_di5 d20 x_di6 c21 x_di7 b21 x_di8 a21 x_di9 d19 x_di10 c20 x_di11 b20 x_di12 a20 x_di13 e17 x_di14 c19 x_di15 d18 x_di16 b19 x_di17 a19 x_di18 c18 x_di19 d17 x_di20 b18 x_di21 a18 x_di22 c17 x_di23 b17 x_di24 d16 x_di25 a17 x_di26 e15 x_di27 c16 x_di28 b16 x_di29 a16 x_di30 d15 x_di31 c15 x_fco b15 x_dclko a15 signal name ball no. x_deno d14 x_do0 e14 x_do1 c14 x_do2 a14 x_do3 b14 x_do4 b13 x_do5 a13 x_do6 c13 x_do7 d13 x_do8 a12 x_do9 e12 x_do10 b12 x_do11 d12 x_do12 c12 x_do13 a11 x_do14 b11 x_do15 c11 x_do16 a10 x_do17 d11 x_do18 b10 x_do19 c10 x_do20 a9 x_do21 b9 x_do22 e10 x_do23 d10 x_do24 c9 x_do25 a8 x_do26 b8 x_do27 d9 x_do28 c8 x_do29 a7 x_do30 b7 x_do31 c7 l_a3 d8 signal name ball no. l_a4 a6 l_a5 b6 l_a6 c6 l_a7 d7 l_a8 a5 l_a9 e8 l_a10 b5 l_a11 a4 l_a12 d6 l_a13 c5 l_a14 b4 l_a15 e6 l_a16 d5 l_a17 c4 l_a18 b3 l_a19 a3 l_a20 a2 reserved b2 vcc e7 vcc e11 vcc e16 vcc e20 vcc g5 vcc g22 vcc l5 vcc l22 vcc t5 vcc t22 vcc y5 vcc y22 vcc ab7 vcc ab11 vcc ab16 vcc ab20 signal name ball no.
mds213 data sheet 16 zarlink semiconductor inc. vdd e9 vdd e18 vdd j5 vdd j22 vdd n22 vdd p5 vdd v5 vdd v22 vdd ab9 vdd ab18 gnd e5 gnd e13 gnd e22 gnd l11 gnd l12 gnd l13 gnd l14 gnd l15 gnd l16 gnd m11 gnd m12 gnd m13 gnd m14 gnd m15 gnd m16 gnd n11 gnd n12 gnd n13 gnd n14 gnd n15 gnd n16 gnd p11 gnd p12 gnd p13 signal name ball no. gnd p14 gnd p15 gnd p16 gnd r11 gnd r12 gnd r13 gnd r14 gnd r15 gnd r16 gnd t11 gnd t12 gnd t13 gnd t14 gnd t15 gnd t16 gnd ab5 gnd ab14 gnd ab22 signal name ball no.
mds213 data sheet 17 zarlink semiconductor inc. 2.0 ball-signal descriptions the type of all pins is cmos. all input pins are 5 volt tolerance. all output pins are 3.3 cmos drive. note: cpu bus interface ball no(s) symbol i/o description g24, g25, g26, h24, j23, h25, k22, h26. j24, k23, j25, j26, k24, k25, l23, k26, m22, l24, l25, l26, m24, m23, m25, m26, n23, n24, n26, n25, p25, p26, p24, p22 p_d[31:0] i/o-ts, u processor data bus data bit [31:0] e24, f23, d26, e26, g23, h22, f24, f25, f26, h23 p_a[10:1] input /out - u processor address bus address bit [10: 1] d25 p_rst# in-st processor bus - master reset f22 p_rwc# input/output- ts, u processor bus - read/write control programmable polarity e23 p_ads# input/output- ts, u processor address strobe d24 p_rdy# out-od- ts, u processor bus - data ready c25 p_brdy# input- ts, u processor bus - burst ready c26 p_blast# input- ts, u processor bus - burst last d23 p_int output processor bus - interrupt request programmable polarity e25 p_clk input processor bus - bus clock a24 p_csi# input- u chip select c24 p_reqc input bus request from cpu - only using in debug mode when system is unmanaged. a26 p_gntc output bus grant to cpu - only using in debug mode when system in unmanaged. a25 p_req1 input/output bus request from secondary mds213 to primary mds213. only using in debug mode when system is unmanaged. e21 p_gnt1 input/output bus grant to secondary mds213 from primary mds213. only using in debug mode when system is unmanaged.
mds213 data sheet 18 zarlink semiconductor inc. # = active low signal input = input signal in-st = input signal with schmitt-trigger output = output signal (tri-state driver) out-od = output signal with open-drain driver i/o-ts = input & output signal with tri-state driver i/o-od = input & output signal with open-drain driver u = internal weak pull-up ts = tri-state st = schmitt trigger frame buffer interface ball no(s) symbol i/o description ab2, ab1, y4, aa3, aa2, aa1, w5, w4, y3, y2, y1, w3, v4, w2, w1, v3, u5, u4, v2, v1, u3, u2, t4, u1, t3, t2, t1, r4, r3, r2, r1, r5, l2, l3, k1, l4, k2, k3, m5, j1, j2, k4, j3, h1, k5, h2, j4, h3, g1, g2, g3, h4, f1, f2, h5, f3, g4, e1, e2, d1, f4, e3, d2, e4 l_d[63:0] i/o-ts, u frame bu ffer - data bit [63:0] a2, a3, b3, c4, d5, e6, b4, c5, d6, a4, b5, e8, a5, d7, c6, b6, a6, d8 l_a[20:3] output frame buff er - address bit [20:3] d3 l_clk output frame buffer clock n2 l_ads# output frame buffer address status control p3, p4, p1, p2, n1, n3, n4, m1 l_bw[7:0]# output frame buffer individual byte write enable [7:0] m3, l1 l_we[1:0]# output frame buff er write chip select [1:0] m4, m2 l_oe[1:0]# output frame buffer read chip select [1:0] ball no(s) rmii ethernet access ports [11:0] ab23 m_mdc output mii management data clock - (common for all rmii ports [11:0]) ab24 m_mdio i/o-ts mii management data i/o - (common for all rmii ports [11:0]) aa4 m_clki input reference input clock
mds213 data sheet 19 zarlink semiconductor inc. ac18, ab17, ae16, ac14, ad13, ae11, af9, ac9, ae6, ac6, af3, ac3 m[11:0]_rxd [1] input-u ports [11:0] - receive data bit [1] ad19, ac17, ad16, af15, af13, af11, ad10, ae8, af6, af4, ae3, ad2 m[11:0]_rxd [0] input-u ports [11:0] - receive data bit [0] ae19, af18, af16, ad14, ac13, ad11, ae9, ad8, ab8, ad5, af2, ab4 m[11:0]_crs _ dv input-u ports [11:0] - carrier sense and receive data valid ad18, ac16, ac15, ae14, ad12, ac11, af8, ad7, af5, ad4, ac4, ab3 m[11:0]_txe n output ports [11:0] - transmit enable af19, ae17, ab15, af14, ae12, ab12, ad9, ae7, ac7, ac5, ad3, ac2 m[11:0]_txd[ 1] output ports [11:0] - transmit data bit [1] ab19, ad17, ad15, ab13, af12, af10, ac10, af7, ad6, ae4, af1, aa5 m[11:0]_txd[ 0] output ports [11:0] - transmit data bit [0] ae18, af17, ae15, ae13, ac12, ae10, ab10, ac8, ae5, ab6, ae2, ac1 m[11:0]_lnk input- st, u ports [11:0] link status gmii gigabit ethernet access port ball no(s) symbol i/o description ae24, af24, aa22, ac23, ad24, af26, ae26, ad26 m[12]_rxd[7: 0] input-u port [12] -- receive data bit [7:0] ad23 m[12]_rx_dv input-u port [12] -- receive data valid ac22 m[12]_rx_er input- u por t [12] -- receive error frame buffer interface (continued) ball no(s) symbol i/o description
mds213 data sheet 20 zarlink semiconductor inc. af20 m[12]_crs input- u port [12] - carrier sense af21 m[12]_col input- u port [12] - collision detected ad25 m[12]_rxclk input- u por t [12] - receive clock ad22, ac21, ae22, af22, ac20, ad21, ae21, ac19 m[12]_txd[7: 0] output port [12] -- transmit data bit [7:0] ae23 m[12]_tx_en output port [12] -- transmit data enable ab21 m[12]_tx_er output port [12] -- transmit error ae20 m[12]_ txclk output port [1 2] - gigabit transmit clock ad20 m[12]_lnk input- st, u p ort [12]--:link status af23 gref_clk input- u port [12] - gigabit reference clock ball no(s) tbi gigabit ethernet access port [12] ad26, ae26, af26, ad24, ac23, aa22,af24, ae24, ad23, ac22 gp_rxd[9:0] input- u port [12] - tbi receive data bit [9:0] af21 gp_rxclk1 input- u port [12] - tbi receive clock 1 ad25 gp_rxclk0 input- u port [12] - tbi receive clock 0 ac19, ae21, ad21, ac20,. af22, ae22, ac21, ad22, ae23, ab21 gp_txd[9:0] output port [12] - tbi transmit data bit [9:0] ae20 gp_txclk output port [12] - tbi gigabit transmit clock ad20 gp_lnk input- st, u port [12] - tbi link status af23 gref_clk input - u port [12] - tbi gigabit reference clock xpipe interface ball no(s) symbol i/o description b23 x_dclki input xpipe data clock input c22 x_deni input xpipe data enable input d22 x_fci input xpipe flow control input gmii gigabit ethernet access port ball no(s) symbol i/o description
mds213 data sheet 21 zarlink semiconductor inc. c15, d15, a16, b16, c16, e15, a17, d16, b17, c17, a18, b18, d17, c18, a19, b19, d18, c19, e17, a20, b20, c20, d19, a21, b21, c21, d20, a22, b22, a23, d21, e19 x_di[31:0] input xpipe da ta input bits [31:0] a15 x_dclko output xpipe data clock output b15 x_fco output xpipe control output d14 x_deno output xpipe data enable output c7, b7, a7, c8, d9, b8, a8, c9, d10, e10, b9, a9, c10, b10, d11, a10, c11, b11, a11, c12, d12, b12, e12, a12, d13, c13, a13, b13, b14, a14, c14, e14 x_do[31:0] output xpipe data output bit [31:0] port mirroring aa26 pm_deni input- ts, u port mi rroring data enable input aa25, aa24 pm_di [1:0] input- ts, u port mirroring input data bit [1:0] y23 pm_deno output port mirroring data enable output ab26, w22 pm_do[1:0] output port mi rroring output data bit [1:0] test facility (sharing pins with othe r functions and for testing purpose only) f15 t_mode# i/o-ts, u test pin - set mode upon reset, and provides test status output. xpipe interface ball no(s) symbol i/o description
mds213 data sheet 22 zarlink semiconductor inc. w22, ab26, y23, aa24, aa25, aa26, w23, y24, y25, y26, w24, u22, v23, w25, w26, v24, u23, v25, v26, u24, u25, r22, t23, u26, t24, t25, t26, r23, r24, r25, r26, p23 t_d[31:0] output test output led interface ac25 le_di input- u led serial data input stream aa23 le_sync# input- u led input data stream ab24 le_clko output led serial interface output clock ac26 le_do output led serial data output stream ab25 le_synco# output led output data stream system clock, power and ground pins ball no(s) symbol i/o description n5 s_clk input system clock at 100 mhz e9, e18, j5, j22, n22, p5, v5, v22, ab9, ab18 vdd power +2.5 volt dc supply e7, e11, e16, e20, g22, l22, t22, y22, ab20, ab16, ab11, ab7, y5, t5, l5, g5 vcc power +3.3 volt dc supply xpipe interface ball no(s) symbol i/o description
mds213 data sheet 23 zarlink semiconductor inc. note: # = active low signal input = input signal in-st = input signal with schmitt-trigger output = output signal (tri-state driver) out-od = output signal with open-drain driver i/o-ts = input & output signal with tri-state driver i/o-od = input & output signal with open-drain driver u = internal weak pull-up ts = tri-state st = schmitt trigger e5, e13, e22, l11, l12, l13, l14, l15, l16, m11, m12, m13, m14, m15, m16, n11, n12, n13, n14, n15, n16, p11, p12, p13, p14, p15, p16, r11, r12, r13, r14, r15, r16, t11, t12, t13, t14, t15, t16, ab5, ab14, ab22 vss power ground ground c1, c1 avdd[1:0] analog power used for the pll a1, a1 avss[1:0] analog ground used for the pll bootstrap pins p23 bs_bmod input cpu bus mode must be set to 0 r26 bs_rw input cpu read/write c ontrol polarity selection default=1 0=r/w#; 1=w/r# r25 bs_swm input switch mode: default=1 0=managed mode 1= unmanaged r24 bs_psd input primary device enable pin default=1 0=secondary 1=primary r23 bs_rdyop input option of merge the p_rdy# and p_brdy# as one pin default=1 0=merged pin 1=separated pins system clock, power and ground pins ball no(s) symbol i/o description
mds213 data sheet 24 zarlink semiconductor inc. 3.0 the media access cont rol (mac) and gigabit (gmac) the mds213 mac/gmac contains twelve fast ethernet ma cs and one gigabit ethernet mac, defined by the ieee standard 802.3 csma/cd. each fast ethernet mac is connected to a physical layer (phy) via the reduced media independent interface (rmii), and the gigabit ethe rnet mac is connected to a phy via the gigabit media independent interface (gmii) or the ten bit interface (tbi ). the mac/gmac sublayer ("mac/gmac") consists of a transmit and receive section and is responsible for data encapsulation/ decapsulation. data encapsulation/ decapsulation involves framing (fra me alignment and frame synchronizati on), handling source and destination addresses, and detecting physical medium transmi ssion errors. the mac/gmac also manages half-duplex collisions, including collision avoidance and contenti on resolution (collision handling). the mds213 includes an optional mac control sublayer ("mac contro l") used for ieee flow control functions. during frame transmission, the mac transmit section enca psulates the data by prepending a preamble and a start of frame delimiter (sfd), inserts a destination a nd source address, and appends the frame check sequence (fcs) for error detection. in vlan aware switches, the mac/gmac inserts, replaces, or removes vlan tags from these frame formats based on instructi ons from the search engine. when necessary, the mac/gmac regenerates the frame check sequence and performs "padding" for frames less than 64 bytes. during frame reception, the ma c receive section verifies that the crc is valid, de-serializes the data, and buffers the frame into the receive fifo. the mac/gmac then si gnals the frame engine, using receive direct memory access (rxdma), that data is availabl e in the fifo and is ready for storage. 3.1 mac/gmac configuration mac/gmac operations are configured through the global device configurat ion register (dcr2) and/or the mac/gmac control and configuration regi sters (ecr0, ecr1), defined in the r egister definition section of the mds213 data sheet. the default settings for autonegotiatio n, flow control, frame le ngth, and duplex mode may be changed and configured by the user on a per-por t basis, either in hardware or software. 3.2 the inter-frame gap the inter-frame gap (ifg), defined as 96 bit times, is the interval between successive ethernet frames for the mac/gmac. depending on traffic conditions, the meas urement reference for the ifg changes. if a frame is successfully transmitted wit hout a collision, the ifg measurement starts from the de-assert ion of the transmit enable (txen) signal. however, if a fr ame suffers a collision, the ifg measur ement starts from the deassertion of the carrier sense (crs) signal. 3.3 ethernet frame limits a legal ethernet frame size, defined by the ieee specification, must be between 64 and 1518 bytes, referring to the packet length on the wire. for transmitting or forwardi ng frames whose data lengths do not meet the minimum requirements, the mac/gmac appends extra bytes (paddi ng) from the pad field. frames, longer than the maximum length may either be forwarded or discarded , depending on the register c onfiguration. although the mac/gmac may be configured to forwar d oversized frames in the device configuration regi ster (dcr2), the frame buffers' maximum size of 1536 bytes cannot be exceeded. for vlan aware systems, the maximum frame size is increased from 1518 bytes to 1522 bytes to accommodate the 4-byte vlan tag. 3.4 collision handling and avoidance in half duplex mode, if multiple st ations on the same network attempt to transmit at the same time, interference could occur causing a collision. the mac/gmac monitors the carrier sense (crs) signal to determine if the medium is available before attempting to transmit data. if the transmission medium is busy, the mac/gmac defers (delays) its own transmissions to decrease the load on t he network. this is ca lled collision avoidance.
mds213 data sheet 25 zarlink semiconductor inc. if a collision occurs, after the first 64 bytes of data, the mac/gmac ceases data transmission and sends the jam sequence to notify all connected nodes of a collision. this jam sequence will persist for 32 bit times. the jam sequence is a 32 bit predeter mined pattern used to notif y other nodes that there is a collision on the network. if a collision occurs during preamble gener ation, or within the first 64 bytes, the transmitter waits until the preamble is completed and then "backs off" (that is, stops transmitti ng) for a specific period (def ined by the ieee 802.3 binary exponential backoff algorithm) before sending the jam sequence and rescheduling transmission. a frame with a size no less than 96 bits (64 bits of preamble and 32 bits of jam pattern), is sent to guar antee that the duration of the collision is long enough to be detected by the transmitting ports involved. 3.5 auto-negotiation the default value of the mds213 mac/gmac enables auto- negotiation. the default value is over written if the phy lacks the ability to support auto-negotiation, wh ich is ascertained through its respective management interface, rmii/gmii. the auto-negotiation process detects the different modes of oper ation (i.e. speed selection, duplex mode) supported by the syste m at the other end of the link segm ent. upon power on/reset, the phy generates a special sequence of fast link pulses (flp s) to begin auto-negotiation. the mds213 mac/gmac, supporting auto-negotiation, reads the results from status register in the phy (10/100 mode) or in the pcs submodule (pcs giga mode). 3.6 vlan support virtual local area networks (vlans) assemble a gr oup of independent ports ( and/or mac addresses) to communicate as if they were on the same physical lan segment, without being re stricted by the physically connected hardware. the ports are logically grouped toge ther by vlan identifiers (vlan ids). the mds213 implements a mac address-based classifi cation that associates each vlan id with its mac address in the switch database memory (sdm) for purposes of aging out, or replacing, old vlans. the mds213 mac/gmac recognizes vlan-tagged frame form ats. during transmission, the mac/gmac inserts (or extracts) the 4-byte vlan tag and regenerates t he frame check sequence for the transmitted frame. vlan support requires an increase in the ma ximum legal frame size, which is set in the device configuration register (dcr2), from 1518 to 1522 bytes. duri ng transmission, if the mac/gmac is re quired to remove the vlan tag from a 64-67 byte rx frame, the ma c/gmac will append extra bytes (pad) to form a 64 byte frame. 3.7 mac control frames mac control frames, as defined by the ieee, are used fo r specific control functions within the mac control sublayer "mac control." similar to data frames, cont rol frames are also encapsulated by the csma/cd mac, meaning that they are prepended by a preamble and star t of frame delimiter and appended by a frame check sequence. these frames may be distinguished from other mac frames by their length/type field identifier (88.08h). the control functions are distinguished by an opcode contai ned in the first two bytes of the frame. upon receipt, mac control parses the incoming frame and determines, by looking at the opcode and the mac address, whether it is destined for the mac (a data frame) or for a specific function within mac control. after performing the specified functions, the mds213 discards all mac control frames it receives, regardless of t he port configuration. these control frames are not forwarded to any other port and are not used to learn source addresses. 3.8 flow control flow control reduces the risk of data loss in the event a long burst of activity causes the mds213 to saturate the buffer memory with backlogged frames. the mds213 suppor ts two types of flow control: collision-based for half- duplex mode and ieee 802.3x flow control for full duplex mode. in both cases, the mds213 recognizes congestion by constantly monitoring available frame bu ffer memory. when the amount of free buffer space has been depleted, the mds213 initiates the flow control mechanism appropriate to the current mode of operation. setting the flow control (fc_enable) bit in the mac po rt configuration register (erc1) turns this operation on, thereby initiating pause frames or applying backpressure fl ow control when necessary
mds213 data sheet 26 zarlink semiconductor inc. 3.8.1 collision-based flow control collision-based flow control, also referred to as backpre ssure flow control, inhibits frame reception for ports operating in half-duplex mode by "jamming" the link. when the free buffer space drops below a user-defined buffer memory threshold, the mds213 sends a jam sequence to al l non transmitting ports, afte r approximately eight bytes of payload data has been received, to generate a collisi on. the jam sequence is a pr edefined serial data stream sent to all ports to indicate that there has been a colli sion on the network. these ports will delay (defer) the transmission of data onto the network until the sequence has been completed. 3.8.2 ieee 802.3x flow control ieee 802.3x flow control reduces network congestion on ports that are operating in full duplex mode using mac control pause frames and is managed by the flow c ontrol management registers. the full-duplex pause operation instructs the mac to enable the reception of frames with a destination address equal to a globally assigned 48-bit reserved multicast a ddress of 01-80-c2-00-00- 01. these pause frames are subsets of mac control frames with an opcode field of 0x0001 and are used by the mac control to request that the recipient stops transmitting non-control frames for a specific period. the pause timer is loaded from the pause frame and is started upon the reception of a pause frame. it will request a length of time for which it wishes to inhibit data frame transmission. in general, the ieee standard allows p ause frames longer than 64 bytes to be discarded or interpreted as valid. the mds213 recognizes all mac control frames (pause frames) between 64 and 1518 bytes long. any pause frames presented to the mac outside of these parameters are discarded. figure 3 - frame with carrier extension and frame bursting mll frame size: 512 bits slot time: 4096 bits fcs coverage late collision threshold: slot time - header size = 4032 bits gmac frame with carrier extension burst limit carrier extension fcs pad data sa da sfd preamble mac frame mac frame interframe mac frame with extension inter frame 65,536 bits carrier event duration gmac frame bursting
mds213 data sheet 27 zarlink semiconductor inc. 3.9 frame bursting at speeds faster than 100mbps and operating in half-dupl ex mode, the mac/gmac can transmit a series of frames without relinquishing control of the transmission medium. this is called frame bursting. frame bursting is utilized when a frame must be extended to the length of the slot time. with frame bursti ng, only the first transmitted frame requires extension. once a frame has been successfully tr ansmitted, the transmit sect ion may submit consecutive frames onto the medium without contention, provided that no idle conditions exist between frames (e.g., no inter- frame gap). the transmitting mac/gmac inserts ext ension bits, detected and extracted by the receiving mac/gmac, into the inter-frame sp ace interval. the mac/gmac may c ontinuously initiate burst frame transmission up to the burst limit of 65,536 bits. 4.0 frame engine description the frame engine is the heart of the md s213. it coordinates all data movement s, ensuring fair allocation of the memory bandwidth and the xpipe bandwidth. when frame data is received from a mac port, it is temp orarily stored in the mac rx fifo until the frame engine moves it to the chip's external memory one granule (128- byte-or-less fragment of frame data) at a time. the frame engine then issues the search engine a switching req uest that includes the source mac address, the destination mac address, and the vlan tag. after the search engine has resolved the address, it transfers the information back to the frame engine via a switching response that in cludes the destination port and frame type (e.g., unicast or multicast). when the destination port is idle, the frame data is fetc hed from the memory and is writ ten to the destination port's mac tx fifo. however, when the destination port is busy transmitting another frame, the frame engine writes a transmission job that includes a frame handle for future id entification. these transmission jobs are stored in the destination port's transmission scheduling queues (txq). there are four txqs per port, one for each priority class. when the destination port is ready, th e frame engine selects the head-of-line jo b from a txq. the frame, specified by the job, will be fetched from the memo ry and will be written to the mac txfifo. for unicast frames, if the destination devic e is local (i.e., the destination port is located in the same device), the frame engine writes a job into th e destination port's transmission schedu ling queue (txq). the transmit dma (txdma) moves the frame data to the mac tx fifo once the frame's transmission job is selected for transmission. if the destination device is remote (i.e ., the destination port is located on anot her device, and can only be reached through the xpipe), all signaling betw een the two devices are sent as xpipe messages. the frame engine sends a scheduling request message via the xpipe to the destination port. this message asks the remote frame engine to write a job into the destination port's txq. when that job is selected, the remote frame engine sends a data request message via the xpipe to the local frame engine. reception of a data request message triggers the forwarding engine module to forward the frame data to the de stination port, one granule at a time through the xpipe until the end of file (eof) safely arrives at the remote port's mac txfifo. for multicast frames, the process is slightly different. th e frame engine uses the vlan index, which is part of the search result, to identify t he destination ports. for local destination port s, the frame engine writes a job to each port's txq. when a transmission job is selected, the txdma moves data from the memory to the mac tx fifo. multicast frame data is sent multiple times, unt il all local destination ports' requests are satisfied. for a vlan that includes remote dest ination ports, the multicast frame dat a is forwarded once through the xpipe and then stored in the remote device's memory. the remote frame engine processes this multicast frame as if it came from a local port. a frame is stored in a frame data buffer (fdb) until it is transmitted. fdbs are ex ternal, located in a mds213's frame buffer memory. to keep track of per-frame control information, the frame engine maintains one frame control buffer (fcb) per frame. fcbs are internal. si nce the frame engine does not access the external memory for frame control information, this conserve s memory bandwidth for better performance.
mds213 data sheet 28 zarlink semiconductor inc. as a frame lives through its lifecycle, its status is updated in the fcb. the fcb also contains vital frame information, such as destination port and length. th ere is a one-to-one correspondence between the fcb and the fdb: fcb#274 contains information about the frame st ored in fdb#274. an fcb/fdb pair is called a "frame buffer," or simply a "buffer." the number 274 is called the handle or the buffer handle. the frame engine takes care of the distribution and the rele asing of buffers. it also keeps buffer counter s to ensure no port or single type of traffic occupies too many buffers. the receiving dma (rxdma) moves frame data from the mac rxfifo to the fdb. before the rxdma writes frame data into the fdb, it must obtain a free buffer handle from the buffer manager. a free buffer handle points to an empty or released frame buffer, ensuring that no stored frame data will get overwritten. after the eof has been safely stored in the fdb, it writes the frame informatio n to the fcb and issues a switching request to the search engine. if the frame is found to be ba d (e.g., bad crc), t he buffer handle will be released and nothing will be written to the search engine or the fcb. this returns the bu ffer back to circulation and the frame is discarded. the rxdma can fail to obtain a free buffer handle for two reasons. all buffers are currently occupied, or the received frame is a multicast frame and the multicast buff er quota is exhausted. in either case, the rxdma will discard the frame, without get ting a handle. if set, the r egister bit dcr2[26], ipmc, enabl es ip multicast privileges. if enabled, the rxdma discards regular multicast frames if the multicast forwarding fifos occupancy exceeds the programmable threshold (see register mb cr[21:20], mcth). an ip multicast frame is discarded only when the multicast frame's forwarding fifo is full. 4.1 transmission scheduling there are four transmit scheduling queues (txq) per port, one for each priority. when a port is ready to transmit, when the previous frame finished transmitting, the port control module notifies t he frame engine. the frame engine selects one txq out of the f our priority queues, depending on the fram e's arrival time and weighted round robin state (refer to the qos chapter for more detail). it reads an entry from the selected transmission scheduling queue, and if the source port of the se lected frame is local, a transmissi on request is issued to the local txdma module. if, on the other hand, the source port is remo te, the data request message is forwarded across the xpipe and subsequently arrives at the forwarding engine. the four transmit scheduling queues per output port al lows the frame engine to perform weighted round robin (wrr) to provide quality of service (qos ). the search engine classifies the fram es into four internal priorities, q0, q1, q2, and q3, in decreasing priority. the 802.1p priority bits are mapped to the internal priorities by a programmable mapping, accessible via register avtc. the user can program the queue weights via register axsc, and thereby control the relative rates of the four internal-priority tagged frames. the maximum txq lengths are programm able from 128 entries to 1024 entries per queue. 52 txqs are located in the external memory. the maximum queue lengths and the base memory addres ses are accessible by the register group {cpuircmd, cpuirdat, cpuirrdy}, under type qcnt. 4.2 buffer management the buffer manager is responsible for the free handle allocation, buffer usage monitoring, buffer release and fcb access control. free handles point to buffers that are not occupied by a fr ame. these free buffers can be allocated to a new frame received by the rxdma. when the frame engine is done processing a frame, its handle is released to the free handle pool. the free handle pool must be initialized via the regi ster group cpuircmd, cpuirdat, cpuirrdy, type bmct, before device operation. the buffer manager control table (bmct) is the pool of free handles. at reset, the bmct is empty. prior to device operation, free handles must be written to the bm ct. the user must write the integers {0,1,2,3, ? k-1} to the bmct one-at-a-time, where k is the maximum number of buffers. the value of k depends on the external memory size and partit ion, and it can be 128, 256, 512, or 1024. if all buffers are used, no more frames can enter the devic e. the frame engine keeps buffer counters that limit the number of buffers occupied by frames destined for each output port. if a buffer counter exceeds a programmable
mds213 data sheet 29 zarlink semiconductor inc. threshold, its associated output port is "blacklisted." ente ring frames destined to this out put port are discarded, until the counter goes below the threshold. this threshold is programmed via registers bct and bchl. these counters prevent complete depletion of buffers due to an over loaded port, thus allow fram es destined for non-congested ports to enter the system. this effe ctively avoids head-of-line blocking. the frame engine also keeps a buffer counter for mult icast traffic types. the buffers occupied by incoming multicast frames are limited. this prev ents multicast frames from blocking unicast ones from entering the system. the threshold for multicast traffic ty pes is programmed via register mbcr. 5.0 frame buffer memory 5.1 frame buffer memory configuration the mds213 system utilizes external sram for its frame buffer memory configuration, where the size of memory supported is ? mb, 1 mb and 2 mb configurations. the foll owing table shows four memory configuration examples for the mds213 system. the following figure shows the connections between t he frame buffer memory and the mds213 for one-bank and two-bank memory configurations. figure 4 - frame buffer memory configuration sram type one bank two bank address size address size 64 kx32 l_a[18:3] ?mb l_a[19:3] 1m 128 kx32 l_a[19:3] 1mb l_a[20:3] 2m table 1 - type and size of memory chips sram 64kx32 sram 64kx32 l_a[18:3] sram 64kx32 sram 64kx32 mds213 l_d[31:0] l_d[63:32] l_a[18:3] one bank 0.5m 64kx32 l_a[18:3] sram 64kx32 sram 64kx32 mds213 l_d[31:0] l_d[63:32] l_a[18:3] one bank 1.5m 128kx32 l_a[19:3] mds213 sram 128kx32 sram 128kx32 l_a[19:3] ce l_d[31:0] l_d[31:0] l_a[18:3] l_d[63:32] l_a[19] ce l_d[63:32] two bank 1m 64kx32 sram 64kx32 sram 64kx32 l_a[19:3] sram 128kx32 sram 128kx32 l_a[19:3] mds213 ce l_d[31:0] l_d[31:0] l_a[19:3] l_d[63:32] l_a[20] ce l_d[63:32] two bank 1m 128kx32
mds213 data sheet 30 zarlink semiconductor inc. 5.2 frame buffer memory usage the mds213 supports two switching modes: managed and unmanaged. the following tables describe frame buffer memory usage for managed and unmanaged modes of operation, respectively. note: fe: frame engine, se: search engine table 2 - frame buffer memory usage for managed mode note: fe: frame engine, se: search engine in unmanaged mode, the system does not support vlan features. thus, vlan related tables are not required. table 3 - frame buffer memory usage for unmanaged mode 5.2.1 memory allocation of a managed system in a managed system, the frame buffer memory is partit ioned into five segments: frame data buffers (fdbs), transmission queues, mailing lists, vlan, and mct vlan association tables. description unit size unit count total size reference by frame data buffer (fdb) 1.5 kbytes 256 to 1 k 384 k bytes to 1.5 m bytes fe 1 transmission queue 4 bytes x 128 k to 4 bytes x 1 k 52 (4 level priority) 26 kbytes to 208 kbytes (at 4 level priority) fe 1 cpu/hisc mailing list 32 bytes to 64 bytes (programmable) 128 to 1k 4 k bytes to 32 kbytes (at 32 bytes each) cpu, hisc & se 1 vlan table 8 bytes x 4 k 1 32 kbytes hisc & se 1 vlan mac table 8 bytes to 32 bytes x 2 k 1 16 kbytes to 64 kbytes hisc & se 1 description unit size unit count total size reference by frame data buffer (fdb) 1.5 kbytes 256 to 1 k 384 k bytes to 1.5 m bytes fe transmission queue 4 bytes x 128 to 4 bytes x 1 k 52 (4 level priority) 13 (1 level priority) 26 kbytes to 208 kbytes (at 4 level priority) fe hisc mailing list 32 bytes to 64 bytes (programmable) 128 to 1 k 4 k bytes to 32 kbytes (at 32 bytes each) hisc & se
mds213 data sheet 31 zarlink semiconductor inc. figure 5 - memory map of managed system 5.2.2 frame data buffers the frame data buffers (fdbs) accommodates the incoming data frames and partitions them into data blocks, where each block occupies 1.5 k bytes. the number of da ta blocks in fdb are configured by setting the value in the register fcbsl[9:0]. since mds213 supports up to 2 m bytes memory, the maximum number of data blocks is 1k. note: the fdb must start at location 0. 5.2.3 transmission queues the transmission queue controls the sche duling of the transmission ports, wher e each of these ports can support up to 4 priorities for each of the 13 ports of the mds213. the number of pr iorities is programmable. thus, the mds213 may be configured for 13, 26, 39 or 52 transmission queues and may support 1, 2, 3 or 4 priority levels, respectively. the size of the transmission queue is 1 28, 256, 512, or 1024 entries and may be setup during the initialization phase. the search engine maintains the contents of each queue, where each queue consists of transmission priorities. each double word (4-bytes) entry contains a fdb handle, which points to the corresponding frame in the buffer. 5.2.4 mailing list the mailing list provides a communi cation channel between the hisc and cpu in managed mode. the size of a mail entry varies, ranging from 32 to 64 bytes, which is det ermined by the initialization setup. when the cpu or the hisc writes mail, the cpu/hisc can obt ain a free mail by the r egister afml that contai ns the addresses of free mail. conversely, when the cpu or hisc reads its mail, the cpu/hisc accesses the mail by the register ambx that contains the address of a cpu/ hisc mail. all of the mail registers are maintained by the hardware. fdb block must start from 0 fdb frame data buffers (1.5kb x # of frame buffers) programmable size 63 0 0 transmission queues (4x13 =52 queues) (each entry = 1dw) (#entry of queue = 128 to 1k) cpu/hisc mailing list (#entry = 128 to 1k) (each mail entry=32 bytes to 64 bytes) vlan table (4k entry, 8b/entry) vlan mac table (2k entry) (each entry=256, 128 or 64 bit) byte 32kb byte byte bytebyte bytebyte byte 7654321 0 programmable size max 16, 32 or 64kb 1/2mb, 1mb or 2mb
mds213 data sheet 32 zarlink semiconductor inc. 5.2.5 vlan table the vlan table associates the ports to their respective vlans, using the vlan id. the table contains 4 k vlan entries, where each entry contains 8 bytes of information. the size of the vlan table is 32 kb (4kx8b). the base address of the vlan table is specifi ed by the vidb in the vtbp bit [5:0]. note: the vlan table must be located at the 32 k boundary. 5.2.6 vlan mac association table the vlan mac table (vlan mct) associates each port' s mac address with its respective vlan. the table comprises of 2048 entries, one entry per mac address. ea ch vlan mac entry is mapped to each bit associated with a vlan specified by the vlan in dex. the size of the tabl e is defined by two bits in the vtbp register and depends on the system configuration (e.g., the number of vlans supported in the system). each entry may consist of 256, 128 or 64 bits (one bit per vlan). the total si ze of the vlan mac table may be 16, 32 or 64 kb. the vmacb field in the register vtbp specifies the base address. note: the vlan mac table must be located at the 16 k boundary. 5.2.7 unmanaged system memory allocation since an unmanaged system does not support vlan operati on, the vlan and vlan mac tables are not required. only the frame data buffers, transmission queues, a nd hisc mailing lists are allocated in system memory. figure 6 - memory map of an unmanaged system 5.3 the frame memory interface 5.3.1 local memory interface each frame within the mds213 is allocated its own buffer memory. the primary function of the frame buffer memory is to provide a temporary buffering space for both received and transmitted frames, as well as frames waiting in the transmission queue. the actual usage depends on the fram e type to be transmitted, either unicast or multicast and the relationship between the source and dest ination ports. the buffer memory also, contains other control structures including stacks, queues, other control tables. the buffer memory may be configured for 128 k, fdb block must start from 0 fdb frame data buffers (1.5kb x # of frame buffers) programmable size 63 0 0 transmission queues (4x13 =52 queues) (each entry = 1dw) (#entry of queue = 128 to 1k) hisc mailing list (#entry = 128 to 1k) (each mail entry=32 bytes to 64 bytes) byte byte byte bytebyte bytebyte byte 7654321 0 programmable size max 1/2mb, 1mb or 2mb
mds213 data sheet 33 zarlink semiconductor inc. 256 k, 512 k, 1024 k bytes depending on the application of the system designer. the mds213 local memory interface supports up to 2 m bytes of sram. 6.0 search engine the search engine is responsible for determining the desti nation information for all packet traffic that enters the mds213. the results from all address or vlan searches are passed to the frame engine to be forwarded, or on to the hisc block for further processing. the result messages to either the frame engine or the hisc provide all the needed information to allow the dest ination block to process the packet. the search engine has been optimized for high throughput searching, utilizing the integrated switch database memory (sdm). the internal sdm contains up to 2 k ma c control table (mct) entries. these mct entries are searched utilizing one of four hashing algorithms that c an be selected. this provides the capability of changing the search hashing to optimize the hash tables based on the tr affic patterns in a given network. for example, if a company gets all their network interface cards (nic) from one vendor, then the source and destination mac addresses will have common fields. this can lead to ineffici ent search hashing. with 4 di fferent hash selections that utilize different parts of the address fields, and can be 8, 9, or 10 bits in length, the hashing algorithm that works best for a user's network can be sele cted (by testing each hash algorithm). figure 7 - typical packet header information the search process begins when the fr ame engine transfers the first 64 byte s of a packet header to the search engine. these bytes are parsed to extract the informati on needed to perform the search for the mct entries that match the source and destination mac address, generate the search hash keys, lookup vlan membership, and other packet status information. destination mac address 0x800 ver 64 bytes layer 1 fcs data sfd preamble packet layer 2 layer 3 layer 4 destination mac address source mac address source mac address vlan tag ihl typ of serv total length identifier fig fragment offset protocol time to live header checksum ip source address options + padding ip destination address source port # destination port # sequence number acknowledgement number offset reserved window u aprsf checksum urgent pointer options + padding data enet 2 header ip header tcp/ip header . . .
mds213 data sheet 34 zarlink semiconductor inc. 6.1 layer 2 search process when the mds213 is in either a "forwarding" state (able to forward packets) or a "learning" state (able to learn new addresses), the search engine is ca pable of performing address searc hes. the search process begins when packet header information is transferred to the search engine from the frame engine. the search engine first checks to determine if the md s213 is configured to support virtual local area networks (vlan). if vlans are enabled, the se arch engine will search for both the destination ma c address, to get destination resolution information, and the source mac a ddress, to get the port's vlan membership and verify the validity of the port's vlan membership. if vlans are di sabled, the search engine will search for the destination and source mac addresses but w ill not do a vlan table check. 6.1.1 vlan unaware when vlans are not enabl ed or configured, the search engine will sear ch the internal switch databas e memory for an mct that matches the destination mac address. when a match is found, the search engine will check to ensure that the destination address is not to be filtered before sending a s earch result message back to the frame engine to start the packet forwarding process. at the same time, a search for the mct that matches the source mac address is also performed. if no match is found fo r the source address, then the source mac address needs to be learned. 6.1.2 vlan aware when vlans are enabled and configured, the search engi ne will begin searching for the destination mct and the source mct. if a matching mct is found for the source address, then no learning is required, and the search engine will check the vlan membership of the source port. if the source port is a member of the vlan, and the destination port is also a member of the vlan, then a normal res ponse message will be passed to the frame engine. if the source port is not a valid member of the vlan, or the destination port is not a member of the vlan, then the search engine will decide to forward the pack et or drop the packet depending upon a user defined configuration. then it will send a message to the hisc to allow the hisc to resolve the issue. 6.2 address and vlan learning address learning can be performed by either the hisc or the search engine and can be enabled or disabled. the global learning control is set in the device configurat ion register (dcr2). the global learning disable (gln) bit controls whether learning is active or disabled, and can be set during initial power up configuration, or by an external cpu before it begins modifying the sdm. it is necessary for an ex ternal cpu to disa ble learning before updating or modifying mct entries. th is prevents the internal learning proc ess from modifying mct entries without the cpu's knowledge. when learning is globally enabled, by the search engine not finding a match to a source address search, it can create a new mct with the necessary information, and then notify the hisc that a new address has been learned. if the search engine request queue be comes 3/4th full, the sear ch engine will ignore address learni ng until the request queue is less full. in that case, packets are forwarded as usual, and a message is sent to the hisc requesting that the hisc l earn the new address. if the search engine request queue is too full, and the hisc request queue is full, then no learni ng will take place. when two mds213 chips are connected, and configured to operate with synchroni zed mct entries, the hisc processor has the ability to send a request to the search engine, instructing it to l earn a new address received from the other mds213. the hisc processor can also use this method to make simple edits to the mct entries for port changes (i.e., source mac address is now co nnected to a different port on the mds213).
mds213 data sheet 35 zarlink semiconductor inc. 6.3 flooding and packet control packets, for which there are no matching destination mct en tries, are by default flooded to all output ports. this can result in broadcast storms and cause the number of flooded packets to increase rapidly. the mds213 provides the user a means for setting a level of flooding, by provid ing a flooding control register (fcr). the fcr allows the user to define a time base (100us to 12.8ms) during which packet flooding at each output port will be counted. three separate flood control fields allo w the user to specify flooding limits for: ? unicast to multicast (flooded) packets per source port ? unicast to cpu packets per chip ? multicast to cpu packets per chip during the time base period, three sepa rate counters at each port count the number of packets meeting the flood control types. once a counter exceeds the allowed quantity, the search engine will t hen discard the packet and any other packets of that type that enter the port dur ing the remainder of the time base period. when the time base period is completed, the three flood counters at each po rt are reset, and the counting process starts over. the flooding control register is global for setting the limit s on all register ports, but the individual ports have separate counters to keep track of the number of flooded. 6.4 packet filtering packet filtering occurs durin g the address search phase. for static sour ce or destination mac address filtering, there is a corresponding bit in the mct entry that tells the search engine that the source or destination packet is to be filtered. when a match is found to a destination mac address s earch, the "destination filter" (d) field in the mct is checked to determine if the destination address is to be fi ltered. if "d" is asserted, th e search engine discards the packet by sending a message to the frame engine telling it to release the frame control buffer (fcb) where the packet has been stored in the frame buffer memory. the packet thereby deleted from memory. when a match is found to a source mac address search, the "source filter" (s) field in the mct is checked to determine if the source address is to be filtered. if "s" is asserted, then the search engine discards the packet by sending a message to the fram e engine telling it to releas e the fcb for the packet. 6.5 address aging entries in the mct database are removed if they have not been used within a user selectable time frame. this aging process is handled by inspecting a single mct entry dur ing each clock period. if the entry is valid and subject to aging, an aging flag in the mct entry is cleared. if the aging flag is already set to ze ro during the inspection, an aging message is sent to the hisc processor to delete and free up the aged mct entry. each time an mct entry is matched by way of a search engine, source search proce ss, the aging flag is asserted to restart the aging process for that entry. some entries may be static and not subject to aging. these mct entries have a status fi eld that identifies them as being static, and will therefore alwa ys have their aging flag asserted. the network manager, using zarlink management software, establishes static entri es during a switch configuration session. 6.6 ip multicast the search engine supports the ability of the mds213 to provide ip multicast by identifying internet group multicast protocol (igmp) packets when parsing the pa cket header information provided by the frame engine. igmp packets are identified when the destination mac address is 01-00-5e-xx- xx-xx, the protocol field has the value of 2, and the source ip address is 224.0.0.x.
mds213 data sheet 36 zarlink semiconductor inc. when an igmp packet is identified, the search engine searches for the source address mct entry, and then passes a message to the hisc to allow it to setup or tear down the ip mult icast session. ip multicast sessions are treated as vlans and use one of the 256 regular vlan entries. 7.0 the high density in struction set computer (hisc) 7.1 description the high density instruction set cpu (hisc) is specif ically designed to implement highly efficient management functions for the mds213 switching hardware, minimizing the management activity intervention during frame processing. the hisc services management requests based on an event-driven approach. management requests can be generated from either the managem ent cpu or the switching hardware. the hisc is also designed with a powerful instruction set and dedicated hardware interfaces for packet processing and transmission to provide high performance packet transfers between t he cpu interface and the switching hardware. 7.2 hisc architecture the hisc is designed with an advanced pipeline architec ture that combines the ad vantages of both risc and vliw architectures. the hisc core combines a rich inst ruction set with 88 general-pur pose registers and support for multiple-way jump. the 88 registers are divided into three parts, eight common gen eral-purpose registers and two banks of 40 registers for two different task contexts. all registers are dire ctly connected to the arithmetic logic unit (alu), allowing two independent registers to be accessed in one single instruction execution. each hisc instruction may have up to three sub-instructions, whic h can be executed in one clock cycle. the resulting architecture is more code efficient while achieving thr oughputs up to ten times faster than a cisc processor or up to three times faster than a risc processor. for a mds213 running at 100 mhz, the hisc can produce up to 300mips processing power. 7.3 hisc operations with an event-driven operation model, upon the request from either the s earch engine or external management cpu, the hisc dynamically manages and maintains the switch database including mac address entries, vlan and mac-vlan association tables. the hisc also pr ovides an external management cpu a high-speed data communication interfaces, so management packets can be transmitted to or received from the network. in general, the service request is received from one of four different sources: ? messages from the management cpu ? requests from the switching hardware (search engine) ?real time clock ? interrupts to the management cpu the hisc performs the following major operations: ? resource initialization ? resource management ? switching database management ? send and receive frames for management cpu 7.3.1 resource initialization the hisc initializes all internal data structures includin g the mail box and switching database data structures, which are used by the management cpu, hisc and switching hardware.
mds213 data sheet 37 zarlink semiconductor inc. 7.3.2 resource management the hisc can enforce a replacement po licy when the number of free data structure for new mac address entries is lower than the predefined threshold. 7.3.3 switching database management one of the major management tasks requ ired of the hisc is to create, de lete, and modify mac address entries upon requests from the search engine or management cp u. generally, the search engine performs the learning of new mac addresses identified in the packet streams. fo r a single mds213 system, the hisc simply informs the management cpu regarding the newly learned mac addresses. the hisc may also create, delete, or modify the mac address en tries based on the requests from the management cpu. for a multi-mds system, the hisc is response for synchronizing the switching databases. in addition to the mac address entries, t he hisc also maintains the following database information required for switching: ? create, delete and modify vlan table in the switching database. ? create, delete and modify mac vlan table in the switching database. ? create, delete and modify ip multicast entries in the switching database. 7.3.4 send and receive frames for management cpu the hisc delivers bdpu, snmp and other frames to and from the management cpu. in unmanaged mode, the hisc also responds to interrupts destined to the management cpu. 7.3.5 communication between hisc and switching hardware high-speed communication channels are required to provide fast message deliveries between the hisc and switching hardware. two high-performance fifos prov ide the required communicat ion channels. they are between the hisc and the frame engine, and between the hisc and search engine. 7.3.6 communication between search engine and hisc the first high-speed fifo is used by the search e ngine to send messages, management requests or received packets, to the hisc. whenever a message is sent to the fifo, the hisc is notified of the new event. each message may contain up to two command codes, processed by the hisc sequentially. the hisc can also request from the search engine to do operations such as search or learn via a hisc i/o interface. after processing the requests, the search engine then sends the response back to the hisc via the fifo. 7.3.7 communication between hisc and frame engine the second high-speed fifo is used by the hisc fo r sending data transfer requests to the frame engine. whenever a packet-forwarding request is received from the management cpu, the hisc forwards the request to the frame engine via the fifo. to alleviate the work load of the management cpu, certain management packets can be processed by the hisc, and then forwarded to the frame engine for tr ansmission via the fifo. 7.4 communication between management cpu and hisc the hisc serves as an intermediary communication channel between the switching hardware and the external management cpu. there are two communication mechanisms provided for messages exchanged between the management cpu and hisc.
mds213 data sheet 38 zarlink semiconductor inc. 7.4.1 cpu-hisc communication using queues the first communication mechanism is a pair of inpu t and output queues between hisc and management cpu. the management cpu input/output queue is a very effici ent mechanism for a single 32-bit data exchange between the hisc and management cpu. in general, a management fr ame, i.e., bridged data protocol units (bdpu), is forwarded directly from the hisc to the managemen t cpu via the cpu output queue. small management requests, less than 24 bits, are delivered to the hisc via the cpu input queue. 7.4.2 mailbox the second communication mechanism is a hardware mailbox that can support variable size messages, exchanged between the management cpu and the hisc. a majo r use of the mailbox is to exchange information required for updating t he switching database. 7.4.3 cpu-hisc mail when the management cpu sends a mail message to the hisc, the cpu acquires an address of a free mail from the free mail list (via register afml). it then writes th e mail content to the given memory address. afterward, it sends the mail to the hisc via the mailbox access (ambx) register. whenever a management mail message is received, an event is generated to inform the hisc to process the mail message. 7.4.4 hisc-cpu mail when a mail message arrives from the hisc, the mailbox hardware sends an interrupt, namely "mail arrive" (mail_arr) to the cpu. the cpu can then access the mail vi a the mailbox access register (ambx). at this point, the cpu reads the mail handle and retrieves the c ontents of the mail from the ambx register. 8.0 the xpipe the xpipe provides a high-speed link between systems ut ilizing two mds213 devices. the xpipe incorporates a 32-bit-wide data pipe, with a high-speed point-to-point connecti ons, and a full-duplex interface between devices. while operating at a 100mhz, this interface can provide 3. 2g bits per second (gbps) of bandwidth per pipe in both directions. 8.1 xpipe connection figure 8 - xpipe system block diagram for the mds213 transmit fifo receive fifo x_do[31:0] x_dclko x_deno x_di[31:0] x_dclki x_deni xmit ctrl rcvd ctrl source receive fifo transmit fifo x_di[31:0] x_dclki x_deni x_do[31:0] x_dclko x_deno x_fci x_fco recd ctrl xmit ctrl x_fco x_fci target target source mds213 mds213
mds213 data sheet 39 zarlink semiconductor inc. the xpipe interface employs 32 data signals and three c ontrol signals for each direction. the pin connections between two mds213 devices are depicted in figure 8. t hese 32 data signals form a 32-bit-wide transmission data pipe that carries xpressflow messages to and from the devic es. the direction of all signals are from the source to the target device, except for the flow control signal, whic h sends messages in the opposite direction; from the target to the source. the three control signals consist of: a tran smit clock signal, a transmit data enable signal, and a flow control signal. the transmit clock signal (x_dclko), provides a sync hronous clock to sample the data signals at the target device. the source device provides the transmit data enable signal (x_deno) t hat envelops an entire xpipe message (including the header and the payload) and is used to identify the message boundary from the received data stream. the timing relationship between the data, clock, and data enable signal s are described in the xpipe timing (section 10.2). the flow control signal (x_fc) monito rs the state of the receiving queue at the target end to prevent xpipe message loss. when the target end does not have enough space to accommodate an entire xpipe message, the target device sends a xoff signal by driving the x_fc o signal to low. the source device will stop further transmission until the x_fci signal asserts the xon st ate, which is an active high (refer to table 4). table 4 - summary description of the source and target end signals the xpipe message header provides the payload size, ty pe of message, routing information, and control information for the xpipe incoming message. the routing information includes the device id and port id. the header size is dependent upon the message types and may be 2 to 4 words in length. figure 9 - xpipe message header 8.2 xpipe timing the source device generates the x_clko signal to provid e a synchronous transmit data clock. the receiver will then sample the data on the falling (negative) edge of the clock, as shown in figure 10. to identify the boundary between the xpipe messages and the data stream, the source device uses the x_deno signal to envelop the entire xpipe message. that is, a rising (positive) edge at the beginning of the first double word signal name description source end target end x_do[31:0] x_di[31:0] 32-bit-wide transm it data bus - includes a xpipe message header and follows by the data payload x_dclko x_dclki transmit clock - synchronous data clock provided by the source end x_deno x_deni transmit data enable - provided by the source end to envelop the entire xpipe message x_fci x_fco flow control signal- a flow control pin from the target end to signal the source end to active xon/xoff. data payload 2-4 words header xpipeflow message header 0-64 words payload
mds213 data sheet 40 zarlink semiconductor inc. (4 bytes) and a falling (negativ e) edge at the beginning of the last double word of an xpipe message as shown in figure 10. note: the negative edge does not occur at the end of the last double word, but instead, at the beginning of the last double word. this allows xpipe messages to be sent consecutively (back-to-back). . figure 10 - basic timing diagram of xpipe 9.0 physical layer (phy) interface the physical layer interface is designed to interface zarlink chipsets to a variety of physical layer devices. reduced media independent interface (r mii) is used for 10/100 interfaces, while gigabit connections can use either gigabit medi a independent interfaces (gmii) or ten bit interface (tbi). the chip ball names for the mac use m as the first letter of the name, followed by thei r pin number, and then their function. for example, m1_rxd0 refers to mac port 1, receive data 0 of the receive data pair. 9.1 reduced mii (rmii) the mds213 implements the reduced media independent interface (rmii) signals, ref_clk, crs_dv, rxd [1:0], tx_en, and txd [1:0], defined in section 5 of the rmii consortium specification. the purpose of this interface is to provide a low cost alternative to the ieee 802.3u [2] mii interface. under ieee 802.3u [2] an mii comprised of 16 pins for data and control is defined. in devices incorporating many ma cs or phy interfaces such as switches, the number of pins can add significant cost as the port counts increase. zarlink mds213 offer 12 or 24 ports, in one or two devices respectively. at 6 pins per port and 1 pin per switch asic, the rmii specification saves 119 pins plus the extra power and ground pins to support those additional pins for a 12 port switch asic. architecturally, the rmii specification pr ovides for an additional reconciliation layer on either side of the mii but can be implemented in the absence of an mii. the management interface (mdio/mdc) is assumed to be identical to that defined in ieee 802.3u [2]. the rmii supports both 10 and 100 mbps data rates across a two bit transmit data (txd) path and a two bit receive data (rxd) path. the rmii uses a single synchronous clock reference s ourced from the media acce ss controller (mac), or an external clock source, to the physical layer (phy). do ubling the clock frequency to 50 mhz allows a reduction of required data and control signals, ther eby providing a low cost alternat ive to the ieee std 802.3u media independent interface (mii). the rmii functions to make the differences between copper and optical phys transparent to the mac sublayer. cycle #1 cycle #2 cycle #3 cycle #4 cycle #5 cycle #6 last cycle idle ......... *1 x_clki/o x_di/o[31:0] x_deni/o d word 0 d word 1 d word 2 d word 3 d word n note 1: positive edge at the beginning of the first double word. negative edge at the beginning of the last double word. ......... ......... .........
mds213 data sheet 41 zarlink semiconductor inc. the rmii specification has t he following characteristics: ? it is capable of supporting 10 mbps and 100 mbps data rates ? a single clock reference is sourced from the mac to phy (or from an external source) ? it provides independent 2 bit wide (di-bit) transmit and receive data paths ? it uses ttl signal levels, compatible with common digital cmos asic processes. rmii specification signals table 5 - rmii specification signals 9.2 the gigabit media independent interface (gmii) the gmii supports the 1000mbps full- duplex operations of the mds213, base d on the media independent interface (mii) defined by ieee std 802.3 (clause 22). the gmii re tains the names and functions of most of the mii signals, but defines valid signal comb inations for 1000 mbps operations. the gmii transfers data in each direction for the data [7:0], delimiter, error, and clock signals. the gmi i implementation extends the transmit data (txd) and receive data (rxd) signals of the mii from four bits wide to eight bits wide and synchronizes the data and the delimiters using a gigabit transmit clock (gtx_clk ) instead of the miis' transmit clock (tx_clk). 9.2.1 the mii management interface the gmii uses the mii management interface is used to control and gather status in formation from the gigabit physical layer (phy) to configure mds213 operations using auto-negotiation. the management interface consists of a pair of signals, called the m_mdio and m_mdc management pins. 9.2.2 mii command and status registers the mds213 utilizes the mii command and status regist ers defined in the 10/100mb ps specification and additional extended registers to support auto -negotiation (ieee std 802.3, claus e 37). the commonality of the mii management registers will allow the mds213 to determine the capabilities supported by the phy and to implement such functions as "start of fr ame" and "determine phy address." 9.3 the physical coding sublayer with ten bit interface (tbi): zarlink mds213 includes the physical coding sublayer (p cs) block. it performs 8b/1 0b conversion between gmii and ten bit interface (tbi). the collision detect (col ) and carry sense (crs) signals are generated from pcs to gmii internally when using tbi interface phy. the pcs bl ock also includes an auto negotiation function. the pcs block can be disabled by us ing the device configurat ion register (dcr2) when gmii interface phy is used. signal name direction (with respect of the phy) direction (with respect to the mac) ref_clk input or output synchronous clock reference for receive, transmit and control interface m[0:11]_crs_dv input carrier sense/receive data valid m[0:11]_rxd[1:0] input receive data m[0:11]_tx_en output transmit enable m[0:11]_txd[1:0] output transmit data m[0:11]_rx_er input (not required) receive error
mds213 data sheet 42 zarlink semiconductor inc. 10.0 the control bus the cpu interface, or control bus, provides the communication path between the system cpu and all other key components within the mds213 (i.e. the hisc). it operat es in two modes: managed mode, where it utilizes an external cpu, and unmanaged mode, where an external cpu does not exist. in managed mode, the cpu interface provides the communi cation path between the sy stems' external cpu and the hisc, frame buffer memory (sram) or another mds213. see figure 11. figure 11 - cpu interface configuration in managed mode in unmanaged mode, the cpu interface provides the co mmunication path between the switch devices and flash memory, and between any two mds213 switches. see figure 12. figure 12 - control bus configuration in unmanaged mode 10.1 external cpu support the control bus comprises of a 32-bit wide cpu bus and supports big and little endi an cpu byte ordering. the standard microprocesso rs supported include: ? intel 486 cpus ? motorola mpc860 and 801 cpus ? intel i960jx cpu ? mips processor with minimum conversion mds213 mds213 cpu flash memory control bus mds213 mds213 flash memory control bus primary dev secondary dev arbitrator
mds213 data sheet 43 zarlink semiconductor inc. 10.1.1 power on/reset configuration on power-up, the following five bootstrap bits, of table 6, are used: table 6 - bootstrapping options 10.1.2 cpu bus clock interface the cpu interface allows the cpu bus clock to operate at clock rates different from the system clock rate. the cpu bus clock rate is always less than or equal to the system clock rate. 10.1.3 address and data buses the cpu interface provides separate, non-multiplexed address and data buses. the data bus is a synchronous, 32-bit bus that can receive 16 or 32-bit wide data. the fl ash memory uses a 16-bit data bus. the data bus supports 32 bit wide data for managed and unmanaged modes. the address bus supports 10 [10:1] address bits for managed and unmanaged modes. each device o ccupies 2048 bytes of input/output space. 10.1.4 bus master the nomenclatures "master" and "slave" refer to the dev ice that possesses the cpu interface, or control bus, while the designations of "primary" and "secondary" refer to the device that possesses the bus arbiter. the primary or secondary device is determined during power on/res et, bootstrap options, while the master or slave device changes dynamically, and will be determined by the arbiter. in managed mode, the systems' external cpu is the perm anent master device. all other devices (e.g., the mds213) are designated as slave devices only. in unmanaged mode, the arbiter (located wi thin the primary device) selects one of the devices as the master. note: in unmanaged mode, the primary device may be the mast er or the slave. the master device is the bus master (controls the bus), while the other device is a slave device. 10.1.5 input/output mapped interface the systems' external cpu accesses the switch devices' lo cal memory using single-read/ write or burst - read/write i/o cycles. burst i/o operations with auto address incrementing uses a 32-byte write data buffer and a 32-byte cache read data buffer. name default functional description bs_bmod 1 bus mode must be 0 bs_rw 1 selects r/w control polarity 0=r/w# 1=w/r# bs_swm 1 switch mode (only in managed mode) 0=managed mode 1=unmanaged mode bs_psd 1 primary device enable (only in unmanaged mode) 0=secondary mode 1=primary mode (the arbiter is activated in t he chip with primary device.) bs_rdyop 1 option of merger the p_rdy# and p_brdy# 0=merged p_rdy# and p_brdy# pin 1=separated p_rdy# and p_brdy# pins
mds213 data sheet 44 zarlink semiconductor inc. 10.1.6 interrupt request the cpu interface accepts an interrupt request (irq) fr om each device connected to the interface, and supports centralized interrupt arbitration a nd vector response. the interrupt output is an open-drain option with programmable polarity. 10.2 control bus cycle waveforms figure 13 - control bus i/o 10.3 the cpu inte rface in unmanaged mode in unmanaged mode, the hisc processor of the master device communicates with the slave device as a cpu function. three regist ers and one flag are used to communicate between the hisc processor and the cpu interface. 10.3.1 arbiter the arbiter of the xpressflow mds213 is an internal logic device used to de termine which device will function as the master device. the connections bet ween the master device, slave device , and the cpu are used for debugging purposes only. see figure 14. write cycle read cycle burst p_clk p_ads# p_rdy# p_a[10:1] p_d[31;0] p_brdy# p_blast# wait wait wait read read read read read one-wait state sample read cycle = 8 clks
mds213 data sheet 45 zarlink semiconductor inc. figure 14 - block diagram of the arbiter note: in unmanaged mode, the cpu is used only for debugging purposes and cannot be involved in switching decisions or management activities. during power on/reset, the bootstrap pi n, bs_psd, determines which device wi ll be the primary and activates the arbiter of that device. at most , three devices, two mds213 devices and one cpu, can operate on the cpu interface at the same time. each device may request access to the cpu interface by sending a request signal to th e arbiter. the arbiter, then sends a grant signal acknowledging which device has been chosen. an arbitrate scheduler, located within the arbiter, decides which device functions as the master device. if the master is the secondary device, the arbiter w ill send a grant signal and a chip select (p_cs) sig nal to the device. if the master is the primary device, the grant signal is sent di rectly to the master state machine (msm) by an internal signal. the scheduler then performs a round robin configuration and allows each device to be the master device. note: during power on/reset, the arbiter always se lects the primary device to be master device. 10.4 cpu interface in managed mode the cpu slave state machine (ssm) accepts address st robe (p_ads#), chip select (p_cs#), and bus-data ready (p_rdy#) signals as ready state signals of a cpu cycle. 10.4.1 cpu access the 32-bit cpu bus interface supports both big and litt le endian cpus. the difference between big and little endian is the byte swapping when cpu writes data to ex ternal memory. table 15 summarizes the byte swapping operation and figure 15 illustrates an exampl e of bytes swapping. figure 15 - little and big endian byte swapping operation if using little endian bit[1] mu st be ?0? for register of mwars, mrars, mwarb, mrarb no byte swapping for cpu data write in or read out to/from mwdr, mrdr registers. if using big endian bit[1] mu st be ?1? for register of mwars, mrars, mwarb, mrarb automatic byte swapping for cpu data write in or read out to/from mwdr, mrdr registers. only for debug cpu mds213 primary mds213 secondary p_gntc p_reqc arbiter master state machine master state machine bus request grant bus chip select p_req1 p_gnt1 p_cs
mds213 data sheet 46 zarlink semiconductor inc. figure 16 - an example of byte swapping 11.0 the led interface 11.1 led interface the mds213 led interface supports the status per port in a serial stream that may be daisy-chained to connect two mds213 chips. daisy-chaining great ly reduces the pin count and number of board traces routed from the physical layer to the leds, thus simplifying system design and reducing overall system cost. for a large port configuration such as the 24+2 in t he mds213, a large number of led signals is needed, which may induce noise and layout issues in the system. the led information is transmitted in a frame- structured format with a synchronization pulse at the start of each frame. figure 17 - led interface connections to provide the port status informati on from our mds213 chips via a serial ou tput channel, five additional pins are required. ? le_clko - at 12.5 mhz ? le_synci/o - a sync pulse -- defines the boundary between frames ? le_di/o - a continuous serial stream of data for all status leds which repeats once every frame time a low cost external device (i.e., a 44-pin fpga-like device) decodes the led framed data and drives the led array for display. this device may be customiz ed for different system configurations. byte 0 byte 1 byte 2 byte 3 cpu bus internal data bus 31 24 23 16 15 8 7 0 byte 3 byte 2 byte 1 byte 0 31 24 23 16 15 8 7 0 mds213 le_synco master le_do mds213 slave le_synci le_di le_clko le_synco le_do led- decoder led-display
mds213 data sheet 47 zarlink semiconductor inc. the port status of the mds213 is transmitted to an exte rnal decoder via a serial output channel. in the mds213, we support cascading of this serial output channel between tw o devices. one mds213 is configured as the master, this initiates the start of led information frames, and seri alizes information bits. the mds213 slave repeats the information sent from the master and appends its own info rmation bits. to cascade these two devices, we will need to extend the number of led pins from 3 to 5. figur e 17 shows two cascaded led interfaces and the connections between the mds213s, the led decoder, and the led display. 11.1.1 function description the led interface employs the following signals: table 7 - led signal names and descriptions 11.1.2 port status in the mds213, each port consists of 8 diff erent led status, represented by separate bits: 1. flow control 2. transmitting data 3. receiving data 4. action (txd or rxd) 5. link up/down 6. speed 7. full duplex/half duplex 8. collision in addition to the 13 ports of the mds213, three extra us er-defined status sets may be sent through the led serial channel for debugging or other applications, where each user -defined status set is also represented by 8 bits. 11.1.3 led interface time diagram the master needs to shift out (13+3)*8 status bits periodi cally. thus, slave needs to shift out (13+3)*8 + (13+3)*8 status bits, which includes the status of the master device and itself. the status of each port will be sample d by the led state machine every 20.5 s, the time period of the frame. that is, each led data frame length equals (256)x 80 nsec. each frame is divided into two subframes: a master and a slave sub-frame. furthermore, each sub-frame is partiti oned into 16 slots (13 mac ports plus 3 user-defined sets) and each slot will carry 8 status bits. the following figu re shows the signal from the slave chip to led decoder. signal name description master device slave device le_clko led clock-synchronous led clock provided by the slave device to led decoder at the system clock divided by 8 (~12.5 mhz). le_synci le_synco a synchronous pulse -- defi nes the boundary between frames. the length of each led data frame is about 256 bits that shift out by le_clko per bit. le_di le_do a continuous serial stream of da ta for all status leds which repeat once every frame time.
mds213 data sheet 48 zarlink semiconductor inc. figure 18 - time diagram of led interface 12.0 data forwarding protocol and data flow 12.1 data fo rwarding protocol 12.1.1 frame reception for normal frame reception, a 128-byte block of frame data is stored in the rx fifo. this block may be shorter if an end of frame (eof) arrives. at that point, the rxdma will request the use of the internal memory bus. when this memory request is granted, the rxdma will move the block from the rxfifo to the frame data buffer (fdb). the mac ports are partitioned into two groups, one for t he gbps port and one for all 12 of the 100 mbps ports. the service discipline is round robin for both the gbps port and 100/10 mbps group. after the entire frame is moved to the frame data buffer (fdb), a switch request will be sent to the search engine (reference search engine section) 12.1.2 unicast frame forwarding for forwarding of the unicast frame, the search engine first resolves the destination device and the destination port, and sends a switch response is sent back to the frame en gine. the frame engine will obtain the type (unicast or multicast), the destinatio n port, and the destination de vice from the search response. after processing the search response, the frame engine will notify the destination port that it has a frame to forward to the destination port's txfifo. for local forwarding (e.g., the destination port is in the local device), the frame engi ne will send the job to the transmission scheduling queue of the destination port. for remote forwarding (i.e., the desti nation port is in the remote device) , the frame engine will create a data forwarding request command message (data_fwd_req), which is sent via the xpipe to the remote device. the remote frame engine, after receiving this data_fwd _req message, will place a job in the transmission scheduling queue of the destination port .the port will serve the next job fr om the transmission scheduling queue when the following two conditions are met: ? it is enough room for a 1.5kbyte frame (a maximum-sized frame) within the txfifo. ? the end-of-frame (eof) of the current frame has arrived at the txfifo. one frame 256x80nsec master dev sub-frame slave dev sub-frame 16 slots 16 slots led_clko cycle #0 cycle #1 cycle #2 cycle #3 cycl e #4 cycle #5 cycle #6 cycle #7 cycle #8 led_synci/o led_di/o p0 bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 bit 0 bit 1 p1 1* one pulse for every 256 cycles
mds213 data sheet 49 zarlink semiconductor inc. there are four transmission-scheduling queues for each por t, one for each of the four classes of priority. the port will send the jobs to the tr ansmission sched uling queues acco rding to a first in fi rst out (fifo) order. to start data transmission, the port obtains a job from the transmission scheduling queue and notifies the transmit dma (txdma) to move the data from the fdb to the mac tr ansmit fifo (txfifo) in 128-byte granules (for local forwarding). otherwise, the device sends a data_req co mmand message via the xpipe to the source device to request remote forwarding. the data forwarding engine modu le in the frame engine of the source device will then forward the frame in 128-byte granules via the xpipe. 12.1.3 multicast frame forwarding after the reception of the switching response, a job is sent to the transmission scheduling queues of the destination ports for local switching. however, for remote switching, one copy of the frame will be forwarded to the remote device in 128-byte granules via the xpipe. this copy of the frame will be sent to the frame data buffer. the frame engine, after the successful reception of this fram e, will put jobs in the tr ansmission scheduling queues of the destination ports of its device. when the txfifo is ready to receive the frame (same as the conditions stated in unica st frame forwarding section), the txdma will forward the frame from the fdb to the dest ination ports in granule form. the maximum size of a granule is 128 bytes. 12.2 flow for data frame the following subsections describe the flow of informatio n during transfers of data frames, both unicast and multicast. 12.2.1 unicast data frame to local device in the simplest case, the data frame is destined for a port on the local device. the frame engine moves the received frame to the local fdb. the search engine form s a switch request with the frame header (includes source mac and destination mac) and passes it to the switch engine to resolve the destination. the switch engine then provides a destination port address to the frame engi ne via a switch response message. frame engine transmits put a transmission job in transmission sc heduling. after the port is ready to send the frame, then frame start to move the frame to txfifo. if the mac address cannot be resolved by the switch engine, the hisc and/or the cpu are queried to resolve the address. for unknown destination mac, the frame will flood the frame into the source vlan domain. 12.2.2 unicast data frame to remote device in the case, the data frame is destined for a port on a remote device. first, the fr ame engine moves the received frame to the local fdb. a switch request with frame h eader (includes source mac and destination mac) is passed to switch engine to resolve the destination. the switch engine then provides a dest ination port address to the frame engine. if the address resolution cannot be comple ted by the switch engine, the hisc and/or the cpu are queried. once the address is resolved, the two frame engines performs the following interactive handshaking procedures via the xpipe: ? source frame engine sends a data forwarding reque st message to destination, where the destination frame engine puts a job in the associated transmission scheduling queue. ? when the destination port is ready to send the frame, the destination frame engine send a data request message to the source frame engine. ? after the source frame engine receives the data request message, it start to move the frame in granule form, which is directly written in the destination txfifo.
mds213 data sheet 50 zarlink semiconductor inc. note that, at the remote device, the frame is written into the transmit fifo of the remo te destination port. the frame is not stored in the fdb of the remote devic e again, so that the latency can be reduce. 12.2.3 multicast data frame in this scenario, we assume that the multicast frame in volve both local and remote ports. the received multicast frame is written to the local fdb by the frame engine. after resolving the destinations, the switch engine then provides local destination port addresses and remote port address to the frame engine. if the address resolution cannot be completed by the switch engine , the hisc and/or the cpu are queried. frame engine pushes the jobs to the corresponding transmission queues (per jo b per local port). when a local port is ready for this multicast frame, the frame engine mo ves the frame to the corresponding txfifo. there is a counter to track of the number of copies to be sent. the number is provided by search engine and the frame engine keeps track of this counter. when a frame is sent, the counter is decreased by one. the fdb will be released when the counter becomes zero. when the destination ports involve remote ports, the fr ame is transferred over the xpipe to the remote frame engine, which writes a single copy of it into the remote fdb. that is we use double store-and-forward for remote multicast. after receiving the whole fram e, the remote frame engine utilizes t he control information in the internal header, which indicates the associated destination ports in the remote device to push the jobs into the corresponding transmission queues. when a port is ready fo r this multicast frame, the frame engine moves the frame to the corresponding txfifo. similarly, the frame engi ne also keeps track of the number of copy of frame to be sent and release the frame when the counter is reduced to be zero. 12.3 flow for cpu control frame in managed system, cpu may transmit or receive cpu cont rol frames, e.g., protocols, snmp frames to/from a mac port via a cpu unicast frame. on the other hand, a cpu may receive a multicast frame from a mac port. moreover, cpu can transmit a multicast frame to multiple por ts. use four scenarios to illustrate the forwarding flow. 12.3.1 cpu transmitting unicast cpu frame the cpu initiates unicast control messages, by first writ ing the frame into the fdb, and then sending a message to the hisc. the hisc forwards a switch response to the fr ame engine, which transmits the frame to the destination mac port. after receiving switch response, frame engine performs the same unicast forwarding as for unicast data frame. refer previous subsection for unicast data frame mechanism. 12.3.2 cpu transmit ting multicast cpu frame when the cpu sends a multicast control message to ports, the cpu first writes the frame to the local fdb. the cpu then sends a message to the hisc, which provides a switch response message to the local frame engine. after receiving switch response, frame engine performs th e same multicast forwarding as for multicast data frame. refer previous subsection for multicast data frame mechanism. 12.3.3 cpu receiving unicast frame the receiving cpu frame is moved to fdb and the fram e engine forwards a switch request including the frame header to search engine. after search engine decodes the header and determines to forward it to hisc to process. hisc informs the cpu via a mail, which indicate s the handle of fdb. cpu then obtains the frame through the mds213. after read the frame from fdb, cpu will inform hisc to rel ease the fdb. finally, hisc passes the release command to frame engine to release the fdb accommodated cpu frame.
mds213 data sheet 51 zarlink semiconductor inc. 12.3.4 cpu receiving multicast frame the mds213 is capable of receiving a multicast packet for a combination of local ports, remote ports, and also the cpu. in this case, the received frame includes multicas t destination ports on a remote device, and also the cpu. the frame engine moves the multicast frame to fdb and t hen form a switch request including the frame header to search engine. since the frame involves cpu, the search engine passes the request to hisc for further process. hisc informs cpu via a mail, which indicates the handle of fdb. in parallel, the search engine sends back a switch response and a sk frame engine to forward the frame to desti nations ports. frame engine will perform the same multicast forwarding as mentioned above. cpu read the frame from fdb via mds213. after read the frame from fdb, cpu will inform hisc to release the fdb. finally, hisc passes the release command to fr ame engine to release the fdb accommodated cpu frame. note that the frame engine won't release fdb until it receiv es the release signal from hisc and also the counter is reduced to zero. that means all the ports and cpu have read out the frame. 13.0 port mirroring 13.1 features the received or transmitted data of any 10/100 port in any mds213 chip, connected by port mirror signal pins, pm_do and pm_di, can be chosen to be mirrored to the "mirror port." the mirror port can be the first port in a mds213 with rmii or a dedicated mirror port with mii, driven by the pin, pm_do[ 0:1]. once the first rmii port of a chip is selected to be the mirror port, it cannot be used to serve as a data port. the configuration of port mirroring is shown in the following diagram, based on the current evalua tion board design. figure 19 - configuration of mirror port for mds213 mds213 chip 0 pm_do[1:0] pm_deno mds213 chip 1 pm_do[1:0] pm_deno pm_di[1:0] pm_deni 4 fe rmii 4 fe rmii 4 fe rmii 1 gmii 4 fe rmii 4 fe rmii 4 fe rmii 1 gmii mii phy port 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 mirror port port mirror port mirror port 0 can be rmii mirror port and mirror port 1-11. port 13 can be a rmii mirror port and mirror port 0-11, 14-24. dedicated mii mirror port can mirror port 0-11, 13-24.
mds213 data sheet 52 zarlink semiconductor inc. 13.2 physical pins there are 6 related pins to port mirroring functions: ? pm_di [1:0] port mirroring input data bit [1:0] receive the mirrored data signal from the remote mds213. ? pm_deni port mirroring data enable signal for pm_di input provide data enable signal for pm_di signals ? pm_do[1:0] port mirroring output data bit [1:0] transmit the mirrored data signal to remote mds213. ? pm_deno port mirroring data enable output. provide data enable signal for pm_do signals refer to figure 20 for connecting above pins. 13.2.1 setting regi ster for port mirroring the apmr register controls the mirrored port, the designated mirroring port. the definition of the register is shown as follows: 13.2.1.1 apmr- port mirroring register bit [11:0]mirr_port10/100 port is chos en to be mirrored, (port bit map) bit [12] local/remoteindicate the mirrore d port from local or remote device. 0=local 1=remote ( note: not support 1g port mirroring.) note that at most only one of bit in bit[11:0] can be set to 1. bit [13] rx/txwhether mirror receiv ing data or transmitting data 0= transmission mirroring, 1=receiving mirroring bit [14] mp0mirror to port 0 (default=0) mp0=1 mirror to port 0 mp0=0 mirror not go to por t 0. i.e., to pm_do pins. bit [31:15]reserve we use examples to illustrate how to set the apmr regi ster. the following examples are based on the configuration of figure 20. 31 0 mp mirror port 0 rx/ tx l/r 15 14 13 12 11
mds213 data sheet 53 zarlink semiconductor inc. example 1: mirroring port 1 to port 0 and mirror transmission direction. for chip 0 set apmr[11:0]=0x002; mirrored port= 1 set apmr[12]=0 ; local mirrored port set apmr[13]=0; trans mission mirroring set apmr[14]=1; port 0 is the mirroring port for chip 1: don't care example 2: mirroring port 1 to port 13 and mirror receiving direction. for chip 0 set apmr[11:0]= 0x002; mirrored port= 1 set apmr[12]=0 ; local mirrored port set apmr[13]=1; receiving mirroring set apmr[14]=0; port 0 is not the mirroring port for chip 1: set apmr[11:0]=0x000 set apmr[12]=1 ; remote mirrored port set apmr[13]=don't carebit[13] has me aning only in the chip of mirrored port set apmr[14]=1; port 13 is the mirroring port example 3: mirroring port 1 to mii mirrori ng port mirror r eceiving direction. for chip 0 set apmr[11:0]= 0x002; mirrored port= 1 set apmr[12]=0 ; local mirrored port set apmr[13]=1; receiving mirroring set apmr[14]=0; port 0 is not the mirroring port for chip 1: set apmr[11:0]= 0x000 set apmr[12]=1 remote mirrored port set apmr[13]= don't carebit[13] has mean ing only in the chip of mirrored port set apmr[14]=0port 13 is not the mirroring port note that cpu needs to find out the sp eed of the mirrored port and configures the mi rroring port to the same speed.
mds213 data sheet 54 zarlink semiconductor inc. 14.0 virtual local area networks (vlan) 14.1 introduction a virtual lan (vlan) is a logical, independent workgroup within a network. the members in this workgroup communicate as if they are sharin g the same physical lan segment. vlan s are not limited by the hardware constraints that physically connect tr aditional lan segments to a network. as a result, vlans can define a network into multiple logical configurations. 14.2 vlan implementation the mds213 based vlan implementation allows up to 256 vlans in one switch. by using explicit or implicit vlan tagging and the garp/gvrp protocol (d efined in ieee 802.1p and 802.1q), vlans may span across multiple switches. a mac address can belong to multiple vlans, and a switch port may be associated with multiple vlans. 14.2.1 static defini tions of vlan membership the mds213 defines vlan membership based on ports. port based vlans are organized by physical port numbers. for example, switch ports 1, 2, 4, and 6 can be one vlan, while ports 3, 5, 7, and 8 can be another vlan. broadcasts from servers within each group would only go to the members of its own vlan. this ensures that broadcast storms cannot cause a network meltdown due to traffic volume. 14.2.2 dynamic lear ning of vlan membership while port based vlan only defines static binding be tween a vlan and its port members, the mds213's forwarding decision needs to be based on the following: ? a destination mac address and its associated port id for a unicast frame, or ? the associated vlan of a source mac address, if t he destination mac address is unknown or it is a multicast/broadcast frame. to make valid forwardi ng and flooding decisions, the mds213 learns the relationship of the mac address to its associated port number and vlan id and builds up the internal switching database at run-time for further use. 14.2.3 dynamic le arning of remote vlan in addition to adding and deleting vlan member ports through network management tools statically, a mds213 based switch can also support gvrp (garp vlan registra tion protocol). gvrp allows for dynamic registration of vlan port members within a switch and across multiple switches. in addition to supporting the dynamic update of registration entries in a switch, gvrp is also used to communicate vlan registration information to other vlan- aware switches, so that a vlan member can be covered by a wide range of switches in a network. gvrp allows both vlan-aware workstations and switches to issue and revoke vlan memberships. vlan-aware switches register and propagate vlan mem bership to all ports belonging to the active topology of the vlan.
mds213 data sheet 55 zarlink semiconductor inc. 14.2.4 mds213 data structures for vlan implementation figure 20 - data structure diagram 14.2.4.1 vlan id table the vlan id table is used by search engine for unicast frames. the base address of this table is specified by vidb subfield in bit[ 5:0] of vtbp register. the contents of this table are set up by the mds213's micr ocode through the command of cpu software at the time of vlan creation and deletion. the vlan id table covers th e entire 4 k vlan id space, and is used by the search engine to map the vlan id into an internal vlan index. it also includes port membership and port tagging information for each vlan. each vlan id entry is 8 bytes long, and the total size of the vlan id table is 32 kb. the vlan id table must be located at the 32 k boundary. figure 21 - vlan id table bit[1:0] p0vlan status for port 0 bit [0]sthis port is a member of this vlan bit [1]ttagout bit[3:2] p1 vlan status for port 1 ?. external ram fdb frame data buffers programmable size 0 fdb block must start from 0 transmission queues cpu/hisc mailing list vlan id table (4k entry, 8b/entry) (2k entry, 256/128/64 bit) byte byte byte bytebyte bytebyte byte 7654321 0 programmable size 64, 32 or 16kb vlan mac table 32kb (up to the number of supported vlan) max 1/2mb, 1mb or 2mb 63 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 9876543210 index[3: 0] index[7: 4] cvp12 p11 p10 p9 p7 p8 p6 p5 p4 p3 p2 p1 t p16 p17 s p28 byte 0 4
mds213 data sheet 56 zarlink semiconductor inc. bit [26]vvlan is valid bit [27]ccpu is a member of this vlan bit [31:28]1st byte: vlan index [3:0], 2nd byte: vlan index [7:4] note: p0 to p12 are used to identify the ports on the first chip , while p16 to p28 are used to identify the ports on the second chip. 14.2.4.2 vlan mac table the size of this table is defined by vlms subfield in bi t[8:7] of vtbp register. the ba se address of this table is specified by vmacb subfield in bit[15:9] of vtbp regist er. the vlan mac table contains all associated vlans for each mac address learned by mds213, and is used by the software to keep track of every mac and its associated vlans. the contents of this table are set up by the search engine at the reception of incoming frames, if the search engine is not fully occupied. when t he search engine is too busy handling frame forwarding decisions, microcode in the hisc engine will be assigned the setup new mac to vlan associations. rows in this table can be cleared up by microcode through a cpu soft ware command during vlan del etion or port link down. a row in this table will be cleared and a new bit set up by the mds213's microcode, when the port change of a mac address is detected. there is a total of 2 k entries in this table, one entry per mac. each entry may consist of 256, 128 or 64 bits, one bit per vlan. the total size of the vlan table may be 64, 32 or 16 kb. this table must be located at the boundary of its own table size. figure 22 - vlan mac table this table can be accessed by cpu software through cpuircmd and cpuirdat registers. mac handle 0 1 2 3 . . . . . . . .. . . 2k 0 1 2 3 ......................... 100 256 vlan id
mds213 data sheet 57 zarlink semiconductor inc. 14.2.4.3 vlan port mapping table (vmap) the vlan port mapping table (vmap) is an internal tabl e within the mds213. it contains 256 entries, one for each vlan, identified by an internal vlan index. the contents of this table are set up and maintained by cpu software during vlan creation, deletion and vlan port memb ership modification. vmap is used by frame engine to forward multicast or destinat ion unknown unicast frames to multiple ports simultaneously. bit [12:0]vlan tag enable [12:0]on e bit for each ethernet mac port 0 = disable, 1 = enable bit [25:13]vlan port enable [ 12:0]one bit for each ethernet mac port, identifying the ports associated with each vlan. 0 = disable, 1 = enable bit [26]re remote ports enable: indi cate some members in the remote device.0=disable, 1=enable bit [31:27]reserve 14.2.4.4 port vlan id (pvid) register this register defines the port vlan id (pvid) and priority for each port. pvid needs to be set up by cpu software, and is used by mds213 to decide the port's vlan id a nd priority if the incoming packet is vlan untagged. bit [11:0]:port vlan id (pvid), bit [12]:reserved bit [15:13]: priority bit [31:16]:reserved 15.0 ip multicast 15.1 introduction ip multicast permits an ip host (source) to transmit a single ip packet to multiple ip hosts (receivers). ip multicasting allows a source to send only one copy and t he network ensures delivery to each member of the specified multicast group. network bandwidth is allocated more efficiently, as multiple copies of the same frame are not transmitted between common ports. the packet destined to an ip multicast group address de termines the set of recipients. hosts may choose to be members of a number of multicasts, and hence select t he multicast packets they wish to receive. they may subscribe or unsubscribe to these multicast groups dy namically, using the internet group management protocol (igmp) that support automatic multicast group membership . igmp is configured to cr eate, update, and/or remove 31 0 re vlan port enable [12:0] 13 12 tag enable [12:0] 27 26 25 31 0 priority 13 12 11 port vlan id 24 23 16 15 8 7
mds213 data sheet 58 zarlink semiconductor inc. dynamic multicast group entries between switches and mu lticast clients and servers. rfc 1112 specifies the protocols and behaviour for ip multicasting. the mds213 supports up to 255 ip multicast groups and tr eats them as extensions of the vlan operation. no additional hardware is needed, since t he igmp operates on the hardware alre ady provided for vlan functionality. igmp packets are identified by the s earch engine and are passed to the ex ternal cpu for processing, when the destination mac address is 01-00-5e- xx-xx-xx, protocol fiel d value equals 2 and the destination ip address is 224.0.0.x. the external cpu then instructs the hisc to setup ip multicast entries for the mac addresses in the switch database memory, the vlan table, and the mct-vlan table. the hisc builds and maintains an mct- vlan and a vlan table for ip multicast groups in the frame buffer memory. when an ip multicast packet is received, it is identified by a specific class of multicast destination mac addresses, where the high-order bits indicate use of igmp, and the low-order bits indica te the specific igmp group identifier. the mds213 searches the mct vlan association table fo r destination mac addresses, using the igmp or the igmp group identifier stored in the mct, to obtain port membership for the ip multicast group. the search engine forwards the packet to each port associated with the ip multicast group. where no address is found, the hisc firmware updates the mct-vlan to include this address. the multicast buffer control register (mbcr) allows th e configuration of multicast frames to be forwarded, the number of buffers reserved for receiving remote multicas t frames, the number of multicast frames allowed, and the multicast forwarding threshold. 15.2 igmp and ip multicast filtering ip multicast filtering optimizes switch ed network performance by limiting multicast packets to only be forwarded to ports containing multicast group membership inst ead of flooding all ports in a subnet (vlan). the internet group management protocol (igmp) runs be tween hosts and their imm ediate neighboring multicast routers. the mechanism of the protocol allows a host to inform its local router that it wishes to receive transmissions addressed to a specific multicast group. routers, also, periodically query the lan to determine if known group members are still active. based on the group membership information, learned from the igmp, a router is able to determine which (if any) multicast traffic needs to be forwarded to each of its "lea f" sub-network. multicast routers use this information, in conjunction with a multicast routin g protocol, to support ip multicasting across the internet. the mds213 based switch supports ip multicast filterin g by passively snooping on the igmp query. the igmp report packets are transferred between ip multicast routers and ip multicast host groups to learn the ip multicast group members within each vlan actively sending out igmp query messages soliciting ip multicast group members. they thus learn the location of multicast r outers and member hosts in multicast groups within each vlan. since igmp is not concerned with the de livery of ip multicast packets across sub-networks, an external ip multicast router will be needed if the ip multicast packets have to be routed across different ip sub-networks. 15.3 implementation in mds213 the mds213 supports up to 255 ip multicast groups and treats them as an extensi on of the vlan operation. no additional hardware is needed, since ip multicast switching/fi ltering already operates in hardware provided for vlan functionality. igmp packets are identified by the s earch engine and are passed to the ex ternal cpu for processing, when the destination mac address is 01-00-5e- xx-xx-xx, protocol fiel d value equals 2 and the destination ip address is 224.0.0.x. the external cpu then instructs the hisc to se tup an mct entry for this ip multicast address in the switch database memory. if this is a new ip multicast group, it sets up an entry in the vlan port mapping table by itself.
mds213 data sheet 59 zarlink semiconductor inc. whenever an ip multicast data packet (destination ma c = 01-00-5e-xx-xx-xx, and desti nation ip address is within the range of 224.0.1.0 and 239.255 .255.255) is received, the search engine will use the mct table to look up the ip multicast address of the incoming packet. frame engine then will use the result from the search (vlan index) to forward this ip multicast packet to its member ports according to the vlan port mapping table. 15.3.1 mct table the mct table is an internal table within the mds213 chip that has a total of 2 k entries. the cpu setups and read the table one entry at a time through microcode in the hi sc. there are two types of overlapped mct entries, one used for layer-2 mac address based unicast switching, and the other for ip multicasting. 15.3.1.1 mct structure for unicast frame the mct table is used by the search engine to forward unicast frames. by looking up a destination mac address from this table, the associated port number is found and used for packet forwarding decisions. the content of the table is set up by the search engine at the reception of an incoming frame, if the search engine is not fully occupied. when the search engine is too busy handling frame forwarding decisions, mi crocode in the hisc engine will be assigned to do the lear ning job by setting up new mac to port associations. an entry in this table can be setup by microcode in hisc through a cpu software command for static layer-2 packet filtering based on either the source or destination address. an entry can be cleared by microcode in the hisc through a cpu software command, during vlan deletion, po rt link down, or when it is aged out. it will also be cleared and a new one set up when a port change of a mac address is detected. t: time stamp, used for aging. set to 1 after mac is found, and cleared to 0 when aged. mac[5:0]:mac address s: source mac address filtering d: destination mac address filtering sp: transmit speed. 1- gbps, 0-100mbps next handle: pointer to the next entry in a hashed link list. 15.3.2 mct structure for ip multicast packet an ip multicast entry in the mct table can be setup or torn down by microcode in hisc through a cpu software command for ip multicasting. whenever an ip multicast dat a packet is received, the search engine will use this table to look up the ip multicast address and vlan id of the incoming packet. if the ip multicast address is found, an internal vlan index from the mct entry will be used by the search engine and frame engine to forward the ip multicast packet to the specific ip multicast group member s in a vlan. if not, the packet will be forwarded to the vlan it belongs to. 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 9876543210 s port number byte 0 8 mac3 mac2 mac1 mac0 t p sd mac5 mac4 next handle 4 12
mds213 data sheet 60 zarlink semiconductor inc. vlan id:the vlan id this ip multicast group is located in. ip[3:0]:ip multicast address vlan index:internal vlan index used to identify this ip multicast group cpu:1: switch cpu is part of this ip multicast group next handle: pointer to the next entry in a hashed link list. 16.0 quality of service (qos) quality of service (qos) provides the capability to rese rve bandwidth throughout the net work. this is particularly useful for sending voice or video over the switched network. in a switched ethernet environment, this is only possible with resource rese rvation protocol (rsvp), a layer 3 protocol . in a layer 2 switch, qos, referred as class of service (cos) by the ieee 802. 1q standard, provides the capability to prioritize certain tasks on the network. this is done at the application level, where appl ications can set the priority when the frame is created. the mds213 classifying ethernet frames according to their i eee 802.1p/q vlan priorities. t here are three bits in the vlan id reserved to designate the priority of a packet. each port stores its transmission jobs into four tr ansmission scheduling queues, one for each priority. before transmitting, a port selects a queue from which a transmissi on job is read. the transmission job points to a frame stored in memory that is fetched and transmitted. the four queues, representing four cla sses of traffic, are selected using a weighted round robin (wrr) strategy. the relati ve service rates among these queues are programmable such that bandwidth can be allocated according to classes. this ensures that critical app lications get a fair share of bandwidth, even when the network is overloaded. the search engine recognizes the ieee 802.1p priority tag and classifies eac h incoming frame into four internal priority classes: p0, p1, p2 and p3, in decreasing priority . since the ieee 802.1p/q allows up to eight priorities, a programmable mapping allows the user to map the 802.1p priority to the inter nal priority tag via register avtc. 16.1 weighted round robin transmission strategy frames of four different priorities are transmitted according to a weighed round robin (wrr) strategy. the wrr is a modified form of the fair round-robin strategy, in which the server visits the queues in turn. in a fair round-robin strategy, the server treats all queues equally and visits them with identical frequency. in a wrr, the queues are weighted, i.e., one queue may be visited more frequently than another. these weighs are programmable via register axsc, in which the service rate ratio between two adjacent classes of traffic is set. in register axsc, setting qsw0=2, qsw1=qsw2=1 gives the service ratio 8:2:1:1, whic h is a good start for most lan switches. this ratio allocates 67% = 8/12 of bandwidth to p0, 16% = 2/12 of bandwidth to p1, and p2 and p3 each receives 8.3% = 1/12 of bandwidth, assu ming all frames have identical frame length. 16.2 buffer management functions the mds213 stores frame data in frame buffers. the num ber of frame buffers in a system is the maximum number of frames a device can store. when all frame buffers are used, incoming fr ames cannot enter the memory and are discarded. without buffer management, a congested port causes a backlog of frames that eventually occupy all 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 9876543210 cvlan index byte 0 8 ip1 ip0 vlan id p ip3 ip2 next handle 4 u 12
mds213 data sheet 61 zarlink semiconductor inc. frame buffers. the mds213 features buffer managemen t functions that prevent a single type of traffic from depleting all frame buffers. the buffer manager limits the number of frames each destinat ion port can store, thereby preventing congested ports from occupying al l the buffers and blocking incoming frames. the buffer manager examines the destination port of ev ery frame stored, and increm ents a counter associated with this destination port. these buffer c ounters keep track of the number of buf fers occupied by frames destined to each port. if the counter reaches a threshold, incomi ng frames destined for the associated port will be dropped. this threshold is programmable via register bct and b chl. register bct allows the user to program two thresholds, one high and one low. the user specifies a threshold, high or low, for each port in register bchl. the buffer manager also prevents multicast frames from occupying all frame buffers. a programmable threshold, register mbcr, limits the nu mber of multicast frames stored in memory . in another word, buffers are reserved for unicast frames.a multicast forwarding job points to a multicast frame in memory fetched and forwarded by the frame engine across the xpipe to the remote device. t he frame engine can only forward a handful of multicast frames simultaneously across the xpipe. excess multicast forwar ding jobs are stored in an internal fifo, called the mc-forwarding-fifo. if the mc-forwarding-fifo is full , incoming multicast frames can no longer be forwarded to the remote device. the mds213 has a programmable option to recognize ip multicast (ipmc) frames. by default, ipmc frames are treated equally with layer 2 multicast frames. this option gives ipmc privilege, in terms of buffer allocation, over regular layer 2 multicast frames. in a broadcast stor m, layer 2 multicast frames are discarded before ipmc frames. the system has the flexibility to recognized a programmabl e ipmc mac addres s signature, set by registers ipmcas0, ipmcas1, ipmcmsk0 and ipcmmsk1. if a pr ogrammable option, dcr2, bit 26, is turned on, the system reserves space in the mc-forwarding-fifo for ipmc frames. this ensures that layer 2 multicast frames do not block ipmc frames. 17.0 port trunking port trunking groups a set of 8 mds213 10/100mbps physical por ts into one logical link; however, all ports in the trunk group must be within the same access device, and each port can only belong to one trunk group. all ports in the trunk group must belong to the same vlan and share th e same mac address. each system can support up to 4 groups. gigabit ports cannot be trunked. load distribution for unicast and multic ast traffic is done based on a hash key, a hash function of the source address and the destination address. 17.1 unicast packet forwarding a trunked port will need to have its ecr1 mac port confi guration register set by cpu software to contain its associated trunk group id. later on, when a new source mac address is learned through that port, the trunk group id will be recorded in the mct entry by either the search engine or the microc ode in the hisc. the trunk group id will be used for forwarding decision when the desti nation mct entry of a received packet is found by the search engine, if the status field indicate s that the address found is on a trunk group. the trunk group id is used by the search engine, along wi th the "hash key" (3 bits result of a hash operation between source address and destination mac address), to ac cess a trunk port mapping table entry in the internal ram. each entry in this table contains the device and port ids for the physical port used to transmit this packet. software needs to set these entries, using tpmxr and tpmtd registers, to distribute th e traffic load across the ports in the trunk group. if the sour ce mac address of an incoming packet is on a trunk group (based on the mct information), the receiving port's tgid will be compared against the trunk group id in the source mct to decide whether the source mac address has moved to another trunk group or not.
mds213 data sheet 62 zarlink semiconductor inc. figure 23 - port mapping table in figure 23, the trunk port mapping table is 32 entries deep (4 groups * 8 hash entries), and each entry is 5 bits wide (1-bit device id, 4-bit port id), as show in the following format. 17.2 multicast packet forwarding for multicast packet forwarding, the destination device must determine the proper set of ports to transmit the packet based on the vlan index and hash key, generat ed by the source search engine. two functions are needed to distribute multicast packets to the ap propriate destination ports in a trunk group. 1. selecting a forwarding port per trunk group: only one port per trunk group will be used to forward mu lticast packets. this can be done with a vlan index table and a forwarding port mask table set up by cpu. 2. blocking multicast packet back to the source trunk: for multicast forwarding that includes ports in trunk groups in the same device as source port, all ports in the same trunk group at the receiving port must be excluded. other wise, this multicast packet will be looped back to the same source trunk group. this is achieved through a tr unk group id register that contains 36 bits (36=12x3). 17.2.1 select one forwarding port per trunk group to forward multicast frames, the fram e engine retrieves the vlan member po rts from one of the 256 entries in the vlan port mapping table (vmap) as described in the vlan section. by us ing the hash key and the forwarding port mask table, the frame engine c an obtain the corresponding fp mask. the final forwarding ports can then be determined by the logical and of the fp mask and the vlan member port bit map. the forwarding port- mask table must be set by the cpu to thkm[0 :7] registers beforehand. th e format of this table and the method of setting it up are shown below. dev id port id (1 bit) (4 bit) tg provided by search eng tg hash key (3 bits) (2 bits) hash keys 32 entries . . . . . . port mapping table for mds213
mds213 data sheet 63 zarlink semiconductor inc. figure 24 - forwarding port mask table two restrictions exist in setting up tables: 1. when setting up the vlan port mappi ng table, all the ports in the trunk gr oup must be set to 1, if the vlan has ports in any trunk group. 2. when setting up the forwarding port mask table, th e cpu software picks only one forwarding port per trunk group. 17.2.2 blocking multicast packets back to the source trunk for local multicast packets, the frame engine needs to block the multicast packets from being sent to the same trunk group as the receiving (source) port. to do it, the se arch engine utilizes the trunk group id (tgid) in ecr1 register. the frame engine compares the tgid of the source an d forwarding ports. if the two tgids are the same, the frame engine blocks the forwarding port for this multic ast packet. the switch engine provides the tgid of the source port. example the following is an example demonstrating this port trunking scheme for multicast packet forwarding: 4 trunk group in a switch: group 0: port 0,1,2 in device 0 group 1: port 4, 5,6 in device 0 group 2: port 1, 2,3 in device 1 group 3: port 4, 5,6 in device 1 a multicast packet with vlan index=5 is received at port 0 of device 0. the membership of this vlan: device 0: port 0,1,2, 4,5, 6, 7 device 1: port 1,2, 3, 4,5,6, 8 3-bit hash key (12 bits) fp mask and 8 entries in table forwarding ports forwarding port mask registers cpu sets up this table as follows: 1. set up one entry of these registers at a time until table is exhausted. 2. set all bits not in any trunk group to 1. 3. set all bits in the trunk groups to 0. 4. pick one forwarding port per trunk group and turn the corresponding bit to 1. (each hash key may have different forwarding port, the rule to pick forwarding port is up to cpu) vlan member port
mds213 data sheet 64 zarlink semiconductor inc. hash key = 3 forwarding port for each group with hash key=3, port 2 for group 0 port 4 for group 1 port 3 for group 2 port 6 for group 3 figure 25 - multicast packet forwarding example 17.3 mac address assignment in mds213, there are three ways to assign the mac address to each port. all the ports in the same device share the 44 msbs, mac[47:4], which are shown in adar0 and adar1 registers, while th e 4 lsbs, mac[3:0] are specified in adaor0 and adaor1 registers for port 0- port 7 and port 8-port 12, respectively. the method to assign the 4 lsbs mac[3:0] can be assigned as follows: ? if the switch does not support port trunking, mac[3:0]= port number ? if the switch supports multiple mac addresses and port trunking, the ports in the same trunk group share the same mac[3:0]. the value of mac[3:0] is assigned by the trunk group (tg) table. ? if the switch supports only a single mac address, all the 4 lsbs of mac will be set the same value in adaor0 and adaor1 register. 18.0 register definitions 18.1 register map all registers are grouped into sets:. ? device configuration ? buffer memory interface ? frame control buffer ? queue management ? switching control ? link list management ? access control functions ? mac port control 0 0 1 1 1 0 0 1 1 1 1 1 1 1 0 0 1 0 0 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 0 0 0 0 0 0 0 0 1 0 0 1 0 1 0 0 0 0 0 0 1 0 1 0 0 1 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 0 0 1 1 1 1 1 1 0 1 0 0 0 0 forwarding port mask vlan member for index=5 for key=3 forwarding ports turn this port off since port 2 has the same tgid of source port 0 0 1 2 3 4 5 6 7 ...........12 0 1 2 3 4 5 6 7 ...........12 device 0 local device 1 remote a n d a n d multicast packet received at port 0 of device 0 vlan idx=5, hash key=3
mds213 data sheet 65 zarlink semiconductor inc. access control: w/r = these register bits may be read from and written to by software w/-- = these register bits may be written to by software, but not read. write only (--/r) = these register bits may be read but not written to by software. read only latched and held bits clear bits permanently set bits all registers are 32-bit wi de. they are classified in the following tables: tag description address w/r 1. device configurat ion registers (dcr) gcr global control register 7c0 w/-- dcr0 device status register 7c0 --/r dcr1 signature & revision & id register 7c4 w/r dcr2 device configuration register 7c8 w/r dcr3 interface status register 7cc --/r memp memory packed register 7dc w/r 2. interrupt controls isr interrupt status register - unmasked 7e0 --/r isrm interrupt status register - masked 7e4 --/r imsk interrupt mask register 7e8 w/r iar interrupt acknowledgement register 7ec w/-- 3. buffer memory interface mwars memory write addr. reg. - single cycle 780 w/-- mrars memory read addr. reg. - single cycle 784 w/-- mwarb memory burst write address register 788 w/-- mrarb memory burst read address register 78c w/-- mwdr memory write data register 790 w/-- mrdr memory read data registers 794 --/r vtbp vlan id & mac member table base pointer 798 w/r mbcr mulitcast buffer control register 79c w/r rama ram block access register 7a0 w/r reserve must set to "0x0001 0008" 7b8 w/r reserve must set to "0x0001 0000" 7bc w/r table 8 - mds213 register map
mds213 data sheet 66 zarlink semiconductor inc. 4. frame control buffers management fcbsl fcb stack size limit 740 w/r fcbst frame ctrl buffer stack - buffer low threshold 744 w/r bct buffer counter threshold 74c w/r bchl buffer counter hi-low selection 750 w/r 5. queue management cinq cpu input queue 708 w/-- cotq cpu output queue 70c -/r 6. switching control hpcr hisc processor control register 6c0 w/r hmcl0 hisc micro-code loading port-low 6c4 w/r hmcl1 hisc micro-code loading port-high 6c8 w/r hprc hisc priority control register 6d0 w/r mcs0r micro sequence 0 register 6d4 w/r mcs1r micro sequence 1 register 6d8 w/r fcr flooding control register 6dc w/r mcat mct aging timer 6e0 w/r tpmxr trunk port mapping table index register 6e4 w/-- tpmtd trunk port mapping table data register 6e8 w/r ptr pacing time regulation 6ec w/r mtcr mct threshold & counter register 6f0 w/r 7. link list management lks link list status register 680 w/r ambx mail box access port 684 w/r afml free mail box list access port 688 w/r 8. access control function group 1 (chip level controls) avtc vlan type code 648 w/r axsc transmission scheduling control register 64c w/r attl transmission timing & threshold control register 650 w/r amiic mii command register 654 w/-- amiis mii status register 658 --/r afcria flow control ram input address 65c w/-- afcrid0 flow control ram input data 660 w/r afcrid1 flow control ram input data 664 w/r tag description address w/r table 8 - mds213 register map (continued)
mds213 data sheet 67 zarlink semiconductor inc. afcr flow control register 670 w/r amar0 multicast addr. for mac control frames byte [3,2,1,0] 674 w/r amar1 multicast addr. for mac control frames byte [5,4] 678 w/r amct mac control frame type code register 67c w/r adar0 base mac address register - byte [3,2,1,0] 600 w/r adar1 base mac address register - byte [5,4] 604 w/r adaor0 mac offset address register port [7:0] 608 w/r adaor1 mac offset address register port [12:8] 60c w/r acktm timer for sof check 610 w/r afcoft10 flow control off time for 10mbps port 614 w/r afcoft100 flow control off time for 100mbps port 618 w/r afcoft1000 flow control off time for giga port 61c w/r afcht10 flow control holding time for 10 port 620 w/r afcht100 flow control holding time for 100 port 624 w/r afcht1000 flor control holding time for giga port 628 w/r 9. access control function group 2 (chip level controls) apmr port mirroring register 5c0 w/r pfr protocol filtering register 5c4 w/r thkm0 trunking forward port mask 0 (hash key=0) 5c8 w/r thkm1 trunking forward port mask 1 (hash key=1) 5cc w/r thkm2 trunking forward port mask 2 (hash key=2) 5d0 w/r thkm3 trunking forward port mask 3 (hash key=3) 5d4 w/r thkm4 trunking forward port mask 4 (hash key=4) 5d8 w/r thkm5 trunking forward port mask 5 (hash key=5) 5dc w/r thkm6 trunking forward port mask 6 (hash key=6) 5e0 w/r thkm7 trunking forward port mask 7 (hash key=7) 5e4 w/r ipmcas0 ip multicast mac address signature low register - byte [3:0] 5e8 w/r ipmcas1 ip multicast mac address signature high register - byte [5:4] 5ec w/r ipmcmsk0 ip multicast mac address ma sk low register - byte[3:0] 5f0 w/r ipmcmsk1 ip multicast mac address mask high register - byte[5:4] 5f4 w/r cfcbhdl fcb handle register for cpu 580 --/r cpuircmd cpu internal ram command register 584 w/r cpuirdat0 cpu internal ram data register - 0 588 w/r tag description address w/r table 8 - mds213 register map (continued)
mds213 data sheet 68 zarlink semiconductor inc. 18.2 register definitions 18.2.1 device configuration register 18.2.1.1 gcr - global control register access: zero-wait-state, direct access, write only address: h7c0 bit [2:0] op-code 3-bit operation control code bit [7:4] syn bits, reserved for hisc usage. cpuirdat1 cpu internal ram data register - 1 58c w/r cpuirdat2 cpu internal ram data register - 2 590 w/r cpuirrdy internal ram read ready for cpu 594 --/r ledr led register 598 w/r 10. ethernet mac port control registers - (s ubstitute [n] with port number, n = {0..12}) ecr0 mac port control register [n*4]0 w/r ecr1 mac port configuration register [n*4]4 w/r ecr2 mac port interrupt mask register [n*4]8 w/r ecr3 mac port interrupt status register [n*4]c --/r ecr4 status counter wrap signal [n*4+1]0 --/r pvidr pvid register [n*4+2]4 w/r op-code command description 000 clr rst clear device reset: - allows state machines to exit from reset state and to initialize their internal control parameters if necessary. 001 reset device reset: -- resets all internal state machines of each device and stays in reset state (except the processor bus interface logic). 010 exec execution: -- allows state machines to start their normal operations. 011 -- no-op 1xx -- no-op table 9 - global control register tag description address w/r table 8 - mds213 register map (continued) syn 24 23 31 20 19 8 7 4 3 2 0 16 15 12 11 op-code
mds213 data sheet 69 zarlink semiconductor inc. 18.2.1.2 dcr0 - device status register access: zero-wait-state, direct access, read only address: h7c0 bit [1:0] status 2-bit operation control code * power-up default = 00 bit [31:2] reserved 18.2.1.3 dcr1 - signature, revision & id register access: non-zero-wait-state, direct access, write/read address: h7c4 18.2.1.4 dcr2 - device configuration register access: non-zero-wait-state, direct access, write/read address: h7c8 status state description 00 init initialization: device is in idle state pending for system software initialization. 01 reset device reset: device is in reset state. 10 exec execution: device is under normal operation. table 10 - device status register bit [3:0] device revision code bit [7:4] reserved bit [15:8] signature 8-bit device signature bit [19:16] reserved bit [24:20] dev_id 5-bit device id ( read/write ) bit [31:25] reserved 31 1 0 status 31 8 7 rev 25 24 20 19 16 15 12 11 4 3 2 0 signature dev_id boot strap 31 fe and mac sc ip 27 26 25 22 21 20 19 18 17 9 8 7 6 5 4 3 2 1 0 mc se configuration mt ml ip
mds213 data sheet 70 zarlink semiconductor inc. sram memory characteristics search engine configuration bit [1:0] sc system clock rate 00= 100mhz 10=90mhz default = 00 01 = 120mhz 11= 80mhz bit [2] ip irq output polarity control 0 = active low output power-up default =0 1 = active high output bit [3] sm system configuration mode 0=nonblocking (for mds213, always equal to 0) 1=blocking bit [4] ml buffer memory level, which can be either 2 chips or 4 chips. 0 = 2 memory chips 1 = 4 memory chips default = 0 bit [6:5] mt memory chip type 00 = 64k x 32-bit 10 = 256k x 32-bit default = 01 01 = 128k x 32-bit 11 = 512k x 32-bit bit [8:7] reserved bit [9] se_agen aging enable, if which is true, the old mct can be aged out. 0 = disable aging default = 1 1 = enable aging bit [11:10] hm hashing mode, each of which uses different bits of mac address to come up with each bit of hashing key. 00=mode 0 0=mode 2 default = 00 01=mode 1 11=mode 3 bit [13:12] hs hashing size 00= 8 10= 10 default = 01 01= 9 11= tdb bit [14] vsw vlan aware switch 0 = vlan unaware default = 0 1 = vlan aware bit [15] noipm no ip multicast 1 = ip multicast disable default = 1 0 =ip multicast enable bit [16] gln global learning disable, where cpu shall disable global learning before look into it as a whole piece. 1 = learning disable default = 0 0 = learning enable bit [17] partial syn enable partial synchronization enable for mac table 0= fully synchronization for mct table default=0 1= partial synchronization for mct table
mds213 data sheet 71 zarlink semiconductor inc. frame engine and mac configuration boot strap determine by the bootstrap value. bit [18] reserved bit [19] fe_agen aging enable. if true, the memory resources, occupied by the old message, will free up. 0 = disable aging default = 1 1 = enable aging bit [20] fof forward oversize frames 0 = discard oversize frames power-up default =0 1 = forward oversize frames bit [21] dec_buffer_cnt decrements buffer count er. when the software writes "1" to this bit, the frame engine decreases buffer counter by one. bit [22] bc_en buffer counter enable 0 = disable (no head of line control 1 = enable bit [23] sta_en status counter enable 0 = collect status in counter disable 1 = collect status in counter enable bit [24] sel_pcs 0 = use external pcs default=0 1 = use internal pcs in the chip bit [25] link_gt tx led will be off when the link is down and this bit is 0 0 = gate 0ff tx_en when link down default =0 1 = not gate off tx_en when link down bit [26] ipmc ip multicast privileges enable: ip multicast traffic has a privilege over regular multicast traffic. 0= disable default=0 1= enable bit [27] bmod control bus mode (read only bit) must be 0 bit [28] rw cpu read/write control polarity selection read only bit 0 = r/w# 1 = w/r# bit [29] swm switching mode (read only bit) 0 = managed mode default=1 1 = unmanaged mode bit [30] psd master device enable (read only bit) 1 =primary default=1 0 = secondary bit [31] mrdy option of merge the rdy and b_rdy as one pin (read only bit) 0 =merged pin default=1 1 = separated pins
mds213 data sheet 72 zarlink semiconductor inc. 18.2.1.5 dcr3 - interfaces status register access: zero-wait-state, direct access, read only address: h7cc bit [3:0] reserved bit [7:4] mem_stat buffer memory interface status bit [4] bb buffer memory busy, cpu interface is busy accessing memory bit [5] re read fifo empty, the fifo that cpu interface reads is empty bit [6] we write fifo empty, the fifo that cpu writes is empty bit [7] res. reserved bit [11:8] que_stat queue manager interface status bit [8] iq_rdy cpu input queue is ready for cpu to write into queue bit [9] iq_full cpu input queue is full bit [11:10] reserved bit [31:12] reserved 18.2.1.6 memp - memory packed register access: non-zero-wait-state, direct access, write/read address: h7dc bit [7:0] rcl read cycle limit (unit is system clock). threshold of reads cycle time. default=16 bit [15:8] wcl write cycle limit (unit is system clock). threshold of writes cycle time. default=16 bit [16] np not packed np=0 enable the feature of memory read/write packed. default=0 np=1 disable, memory access will be a pure round-robin scheme. bit [31:17] reserved 31 4 3 2 1 0 12 11 que_stat 25 24 21 20 16 15 8 7 mem_stat 31 - 30 5 wcl 17 16 15 8 7 rcl 0 np
mds213 data sheet 73 zarlink semiconductor inc. 18.2.2 interrupt control registers four 32-bit control registers. isr interrupt status registeridentify t he unmasked interrupt request sources access: zero-wait-state, direct access, read only address: h7e0 isrm masked interrupt status reg.identify the sources of interrupt with masking ? access: zero-wait-state, direct access, read only ? address: h7e4 imsk interrupt mask registerdefines the interrupt sources to be masked ? access: non-zero-wait-state, direct access, write/read ? set bits to 1 to mask the corresponding interrupt sources ? address: h7e8 iar interrupt acknowledgment reg.cl ear the interrupt request bits ? s access: non-zero-wait-state, direct access, write only ? s set bits to 1 to clear the corresponding interrupt sources ? s address: h7ec all 4 registers have a common regi ster format and bit assignment interrupt sources (the followi ng bits need to be redefined.) bit [0] cpu_q_out cpu output queue level interrupt bit [1] bsr bad switch response bit [2] double r double release bit [3] fcb_low fcb low bit [4] hisc_bp hisc instruction pointe r matched with breakpoint register bit [5] reserved bit [6] reserved bit [7] mail_arr mail arrived from hisc bit [8] hisc_to hisc timeout interrupt bit [9] reserved bit [10] fml_av link manager informs cpu that at least 16 free mail entry available after cpu encounters empty free mail list situation. bit [23:11] mac_port interrupt from mac ports bit [11] for port 0, bit [12] for port 1 ? bit [23] for port 12, port 12 is a giga port 31 11 10 9 8 7 6 5 4 3 2 1 0 interrupt mac port mapping bit/port 25 24 23 interrupt source mc t mac_port interrupt fm l hi sc ma il bpfc il db r bs r cp q
mds213 data sheet 74 zarlink semiconductor inc. bit [24] mct search engine found looped mct chain. bit [31:25] reserved note: mail_arr, cpu_q_out and interrupts cannot be cleared by the cpu. they will be cleared whenever their queues are emptied. 18.2.3 buffer memory interface register 18.2.3.1 mwars - memory write address register - single cycle access: zero-wait-state, via fifo, write address: h780 bit [0] lk lock flag (for internal memory only)lk=0 unlocklk=1 lock bit [1] sp swap byte order bit [20:2] ma [20:2] buffer memory ad dress bit [20:2] - (bit [1:0] = 00) bit [21] reserved bit [22] i/e indicates the address is internal or external memory i/e=0 internal memory i/e=1 external memory bit [27:23] count must be 00001 bit [31:28] be [3:0] byte lane enables 18.2.3.2 mrars - memory read address re gister - single cycle access: zero-wait-state, via fifo, write address: h784 bit [0] lk lock flag memory lk=0 unlock lk=1 lock bit [1] sp swap byte order bit [20:2] ma [20:2] buffer memory address bit [20:2] - (bit [1:0] = 00) bit [21] reserved bit [22] i/e indicate the address is internal or external memory i/e=0 internal memory i/e=1 external memory cpu bus type bit [31] bit [30] bit [29] bit [28] little endian be [3] be [2] be [1] be [0] big endian be [0] be [1] be [2] be [3] 31 3 2 1 0 address ma[20:3] 28 27 26 24 23 22 21 20 sp be[3:0] 00001 i/e lk address ma[20:2] 24 23 22 21 20 sp be[3:0] 00001 i/e lk 31 3 2 1 0 28 27
mds213 data sheet 75 zarlink semiconductor inc. bit [27:23] count must be 00001 bit [31:28] be [3:0] byte lane enables 18.2.3.3 address registers for burst cycle two 32-bit burst size registers share a common format ? mwarb memory address register - burst write (in d-words) - maximum 8 d-words ? address: h788 ? mrarb memory address register - burst read (in d-words) - maximum 8 d-words ? address: h78c access: zero-wait-state, via fifo, write bit [0] lk lock flag lk=0 unlock lk=1 lock bit [1] sp swap byte order bit [2] reserved bit [20:2] ma [20:2] buffer memory address bit [20:2] - (bit [1:0] = 00) bit [21] reserved bit [22] i/e indicate the address is internal or external memory i/e=0 internal memory i/e=1 external memory bit [27:23] count count = burst size in double words burst size for internal memory is up to 8 d-words. burst size for exte rnal memory is up to 16-dwords 00001 = 1 d-word, ??01000 = 8 d-word 01111 = 15 d-word 10000= 16 d-word valid value range for internal memory is {1 to 8} valid value range for external memory is {1 to 16} caution: when setting count = 16, the star ting address has to be in the q-word boundary. that is ma[2]=0. bit [31:28] reserved address ma[20:2] 24 23 22 21 20 sp count i/e lk 3 2 1 0 28 27 31
mds213 data sheet 76 zarlink semiconductor inc. 18.2.3.4 memory read/write data registers four 32-bit data registers share a common format ? mwdr memory write data register ? access: zero-wait-state, via fifo, write only ? address: h790 ? mrdr memory read data register ? access: zero-wait-state, direct access, read only ? address: h794 byte order depends on cpu types ? little endian cpus ? big endian cpus 18.2.3.5 vtbp - vlan id table base pointer access: non-zero-wait-stat e, direct access, write/read address:h798 bit [5:0] vidb vlan id table base, se rves as [20:15] bits of address. (vlan id table is 32kb) bit [6] reserved bit [8:7] vlms the size of vlan mac table default=11 00= reserved 01=16k (for 64 vlans) 10=32k (for 128 vlans)11=64k (for 256 vlans) bit [15:9] vmacb vlan mac table base, serves as [20:14] bit of address. this table indicates the associ ation of mac address and vlan bit [31:16] reserved 24 23 byte [3] 0 31 byte [2] byte [1] byte [0] 16 15 8 7 24 23 byte [0] 0 31 byte [1] byte [2] byte [3] 16 15 8 7 31 0 11 10 9 8 7 6 5 vmacb 17 16 15 vlan id base vlms
mds213 data sheet 77 zarlink semiconductor inc. 18.2.3.6 mbcr - multic ast buffer control register access: non-zero-wait-state, direct access, write/read address: h79c bit [4:0] max_mc_fd maximum number of mu lticast frames allowed for forwarding bit [10:5] rmc_buf_rsv number of buffers reserved for receiving remote multicast frames bit [19:11] max_cnt_lmt maximum number of multicast frames allowed per device bit [21:20] mcfth multicast forwarding thres hold: watermark for forwarding ff to drop regular multicast packet if ipmc bi t in dcr2[26] is on. cpu can set four level watermarks, which are programmable 00= 25% 01=50% 10= 75% 11= 100% bit [31:22] reserved 18.2.3.7 ama - ram counter block access register access: non-zero-wait-state, direct access, write/read address: h7a0 ram counter block contains 13 counter blocks (one for each port) port 0 counter block starts at address 0.) the size of each block is 16 double words, which consist of total 30 statistic counters. has total the size and type of each counter is referred to the register ecr4. cpu uses this register to access the specified statistic counter by setting the start address of ram counter block and the length. bit [3:0] bst_cnt read/write burst (length) of ram block. (unit = 1double words) bit [10:4] st_adr read/write start address. bit [14:11] reserved bit [15] w/r ram block access write/read indicator 1 = write 0 = read bit [31:16] reserved note: the access range is equal to from st_adr to end_adr= s_adr+ bst_cnt. the end_adr cannot cross the boundary of each port bl ock, i.e., 8 double words. 31 0 11 10 mcth 22 21 20 19 5 4 rmc_buf_rsv max_cnt_lmt max_mc_fd 31 0 11 10 w/ 16 15 14 bst_cnt st_adr r 4 3
mds213 data sheet 78 zarlink semiconductor inc. 18.2.3.8 reserve register 1 access non-zero-wait-state direct-access write/read address: h7b8 must be set to "0x00010008" 18.2.3.9 reserve register 2 access non-zero-wait-state direct-access write/read address: h7bc must be set to "0x00010000" 18.2.4 frame control buffers management register 18.2.4.1 fcbsl - fcb queue access: non-zero-wait-state, direct access, write/read address: h740 bit [10:0] defines max # of fcb buffers size range: 1 entry, to 1024 entries bit [17:11] aging timer base defines the time interval between scanning of fcb buffers for aged buffers aging time = (number of valid fcb buffers* aging timer base) msec 18.2.4.2 fcbst - fcb queue - buffer low threshold access: non-zero-wait-state, direct access, write/read address: h744 bit [5:0] buf_low_th buffer low threshold - the number of frame control buffer handles left in the queue to be considered as running low and trigger the interrupt to the cpu. bit [31:6] reserved 0x0008 0x0001 31 16 15 4 3 2 1 0 0x0000 0x0001 31 16 15 3 2 1 0 25 0 max # of fcb buffer aging timer base 31 18 17 11 10 blowth 0 31 6 5
mds213 data sheet 79 zarlink semiconductor inc. 18.2.4.3 bct - (fcb) buffer coun ter threshold access non-zero-wait-state direct-access write/read address: h74c bit[9:0] low_limit low limit number of frames to each destination port (i.e., source port limits the # of fcb used by each destination port) bit[19:10] hi_limit high limit number of frames to each destination port (i.e., source port limits the # of fcb used by each destination port) 18.2.4.4 bchl - buffer counter hi-low selection access non-zero-wait-state direct-access write/read address: h750 bit[12:0] lp_hi_low sel selection for low or hi gh limit of buffer counter for local device 13 bits maps to 13 ports in local device 1 = select hi limit 0 = select low limit bit[25:13] rp_hi_low sel selection for low or hi gh limit of buffer counter for remote device 13 bits maps to 13 ports in remote device 1 = select hi limit 0 = select low limit 18.2.5 queue management register 18.2.5.1 cinq - cpu input queue access: non-zero-wait-state, direct access, write only address: h708 note: check iq_rdy=1 in dcr3 (interface status register) before writing into cpu input queue low limit 0 31 19 10 9 hi limit 0 31 25 13 12 rp_hi_low sel lp_hi_low sel 0 31 32-bit data from cpu input queue
mds213 data sheet 80 zarlink semiconductor inc. 18.2.5.2 cotq - cpu output queue access: non-zero-wait-state, direct access, read only address: h70c bit [30:0] 31-bit cpu output queue entry bit [31] status queue is ready 18.2.6 switching control register 18.2.6.1 hpcr - hisc processor control register access: non-zero-wait-state, direct access, write/read address: h6c0 bit [0] ht halt the hisc processor from execution not apply for non-managed mode (it can be fixed in next cut.)power-up default = 1 bit [1] ld switch the micro-code memory from instruction fetch mode to down- loading mode bit [2] rs reset ip to 0 - ( write only bit ) (this bit is auto reset to 0 after ip is reset to 0) bit [31:3] reserved rs ld ht state description 101 init initialization state : -- stopped hisc execution, reset ip to 0. 001 halt halt state : -- stopped hisc execut ion, waiting for ht=0. 01x load micro-code loading state : -- stopped hisc execution, increment ip for every wr/rd to hmpc 100 start start state : -- reset ip=0, and start hisc execution. 000 exec execution state : -- continue hisc execution without reset ip. 11x -- illegal state . 0 31 30 cpu output queue entry 3 2 1 0 31 rs ld ht
mds213 data sheet 81 zarlink semiconductor inc. 18.2.6.2 hmcl0 - hisc micro-code loading port - low access: non-zero-wait-state, direct access, write/read address: h6c4 loading micro code into hisc. bit [31:0] hisc instruction word [31:0] hisc in struction word has total 40 bit-wide. needs to be broken into two registers. 18.2.6.3 hmcl1 - hisc micro-code loading port - high access: non-zero-wait-state, direct access, write/read address: h6c8 bit [7:0] hisc instruction word [39:32] bit [31:8] reserved 18.2.6.4 ms0r micro sequence 0 register access: zero-wait-state, direct access, write/read address: h6d4 bit [31:0] data bit [31:0] to the sequencer ram (the length of micro sequence data is 54-b it, need to be broken into tow registers) 18.2.6.5 ms0r micro sequence 1 register access: zero-wait-state, direct access, write/read address: h6d8 bit [19:0] data bit [51:32] to the sequencer ram bit [31:29] cnt control bits (write only bits) 000 nop 0 31 hisc instruction word [31:0] 19 0 hisc instruction [39:32] 31 8 7 0 31 databit[31:0] 16 15 24 23 8 7 0 data bit[51:32] 31 29 28 cnt 20 19
mds213 data sheet 82 zarlink semiconductor inc. 001 load 010 restart ptr 011 incadr 100 halt 101 unload 110 unhalt bit [28:20] reserved 18.2.6.6 flooding control register access: non-zero-wait-state, direct access, write/read address: h6dc bit [7:0] m2cr multicast to cpu rate restricts the number of frames within the time window defined in bit[15:12] bit [11:8] u2mr unicast to multicast rate restricts the number of flooding unic ast frames within the time window bit [14:12] time base defines the time window used by m2cr and u2mr 000 = 100us 001 = 200us 010 = 400us 011 = 800us 100 = 1.6ms 101 = 3.2ms 110 = 6.4ms 111 = 100us bit [15] reserved bit [23:16] u2cr unicast to cpu rate restricts the number of frames within the time window defined in bit[15:12] bit [31:24] reserved 18.2.6.7 mcat - mct aging timer access: non-zero-wait-state , direct access, write/read address: h6e0 bit [19:0] when the value is reached, it ages out default=0 msec (unit=msec) must be configured to not zero value. suggestion value: 5msec. 0 unicast to cpu rate 31 24 23 time 16 15 14 8 7 base u2mr multicast to cpu rate 12 11 0 mct aging timer 31 20 19
mds213 data sheet 83 zarlink semiconductor inc. 18.2.6.8 tpmxr ? trunk port mapping table index register access: non-zero-wait-state, direct access, write/read address: h6e4 for trunk port mapping table pointer bit [7:0] 8-bit table entry index bit [31:8] reserved value set to 0 18.2.6.9 tpmtd - trunking port mapping table data register access: non-zero-wait-state , direct access, write/read address: h6e8 bit [3:0] port id trunking port bit [4] dv device id bit [31:5] reserved 18.2.6.10 ptr - pacing time regulation access non-zero-wait-state direct-access write/read address: h6ec use for pacing traffic to remote ports vi a xpressflow pipe or local transmission bit [3:0] 100_tm 100m port timer default =5 bit [7:4] g_tm gigabit port timer default =6 bit [11:8] mc_tm multicast timer default =5 bit[ 15:12] uc_tm unicast timer default =5 unit time = 80 nsec.(for 64 bytes frame.) note that frame engine determine the tic value dependent upon the frame. if s hort frame, it takes above value. for long frame (> 64 frame), it will do uble the above value as the reference. bit [31:16] reserved 0 entry index 8 7 31 0 port id 31 dv 4 3 5 0 100_tm 31 15 12 11 g_tm 4 3 uc_tm mc_tm 8 7 mc_tm 16
mds213 data sheet 84 zarlink semiconductor inc. 18.2.6.11 mtcr - mct threshold & counter register access: non-zero-wait-state, direct access, write/read address: h6f0 bit [10:0] reserved bit [21:11] mct threshold alert system when free mct entries are below this threshold bit [31:22] reserved 18.2.7 link list management 18.2.7.1 lks - link list status register access: zero-wait-state, direct access, read only address: h680 bit [0] mail box is not ready for cpu to send entry to hisc 1=not ready0=ready bit [1] free mail box is not ready for cpu to put entry into 1= not ready0=ready bit [2] cpu gets mail from hisc 1= ready0=not ready bit [3] free mail box has entry for cpu to get 1=ready 0=not ready bit [31:4] reserved 18.2.7.2 ambx - mail box access port access: zero-wait-state, direct access, write/read address: h684 in write mode, cpu sends mail to hisc in read mode, cpu receives mail from hisc 0 31 mct threshold 11 10 22 21 0 31 3 4 1 2 0 31 20 entry handle 30 0 0 0 1 21 2
mds213 data sheet 85 zarlink semiconductor inc. bit [20:0] entry handle, the bit [2:0] always 2'b000 bit [29:21] reserved bit [30] link list is empty. ( read only ) bit [31] link list is ready. (same as bit [0] of lks register) ( read only ) 18.2.7.3 afml - free mail box list access port access: zero-wait-state, d irect access, write/read address: h688 bit [20:0] entry handle, the bit [2:0] always 2'b000 bit [29:21] reserved bit [30] link list is empty. ( read only ) bit [31] link list is ready. (same as bit [1] of lks register) ( read only ) 18.2.8 access control function 18.2.8.1 avtc - vlan type code register access: non-zero-wait-state, direct access, write/read address: h648 bit [15:0] 2-byte vlan type code defined by ieee 802.1q vlan standard bit [31:16] priority 4 level priori ty denoting by 2-bit for each mapping 8 level vlan priorities to 4 level internal priorities. 18.2.8.2 axsc - transmis sion scheduling control register access: non-zero-wait-state, direct access, write/read address: h64c 0 31 20 entry handle 30 0 0 0 1 21 2 0 31 16 15 vlan type code p7 p6 p5 p4 p3 p2 p1 p0 0 qsw0 31 12 11 qsw1 4 3 qsw2 8 7
mds213 data sheet 86 zarlink semiconductor inc. bit [11:0] qsw[2:0] transmission queue service weight for queue 2, 1 & 0. (4 bit each) defines the service rate for each queue qr0-qr3 qr0 : qr1 : qr2 : qr3 qr0 = qsw0*(qsw1+1)* (qsw2+1) qr1 = qsw1*(qsw2+1) qr2 = qsw2 qr3 = 1 note: queue 0 has the highest priority. queue size is defined in the queue control table 18.2.8.3 attl - transmission timing control access: non-zero-wait-state, direct access, write/read address: h650 bit [4:0] transmission queue aging time out counter bit[13:5] frame latest departure time bit [21:14] txfifot transmission fifo threshold in bytes (default =0) only for 100 m ports unit=8bytes 0= cut through at t he destination 100 m port when the value does not equal zero, it indicates the port cannot start sending frames out, until the tx fi fo reaches the threshold or eof. 18.2.9 mii serial management channel these registers are part of the management module. they allow the upper layer services to communicate with any one of the phys that are connected to the ma nagement module through the serial interface. 18.2.9.1 amiic - mii command register this is a write-only register. the upper layer services writ e the management frame to be sent to the phys into this register. the msb (bit 31) is the first bit sent over the serial interface. access: non-zero-wait-state, direct access, write only address: h654 bit [31:30] st start of frame - always = "01" bit [29:28] op operation code - "10" fo r read command and "01" for write command bit [27:23] phy_ad 5-bit phy address 0 qmt_cnt 31 14 13 depart_time 5 4 txfifo threshold[7:0] 22 21 2 1 0 reg_ad 23 22 data (16-bit) st op phy_ad ta 31 30 29 28 27 18 17 16 15
mds213 data sheet 87 zarlink semiconductor inc. bit [22:18] reg_ad 5-bit register address in phy bit [17:16] ta turnaround - "10" for write bit [15:0] data 16-bit write data to phy 18.2.9.2 amiis - mii status register the upper layer services should read this register for data sent by the ph ys. the lower 16 bits contain data received by the management module access: non-zero-wait-state, direct access, read only address: h658 bit [31] rdy data ready bit [30] valid data valid bit [15:0] data 16-bit read data from phy 18.2.10 flow control management 18.2.10.1 afcria - flow control ram input address access: non-zero-wait-state, direct access, write only address: h65c bit [2:0] 3-bit address for the ram in mac storing fl ow control frame usage: flow control frame consists of 64 bytes. usin g afcria and afcrid0-1, the cpu loads 8 bytes each time. the cpu specifies the address in afcria and writ es the content of 4 bytes in afcrid0 and 4 bytes in afcrid1. then repeats the above procedure 8 times to load a whole flow control frame into the chip. bit [31] rdy bit [30] valid description 1 1 data field contains valid data from the phys 1 0 data field contains invalid data from the phys 0 x data field is not ready to be read by switch manager cpu 2 1 0 data (16-bit) ry vd 31 30 29 16 15 0 address 31 3 2
mds213 data sheet 88 zarlink semiconductor inc. 18.2.10.2 afcrid0 - flow control ram input data 0 access: non-zero-wait-state, direct access, write only address: h660 bit [31:0] content of flow control frame [31:0], flow control frame has 64 bytes and is defined by ieee 18.2.10.3 afcrid1 - flow control ram input data 1 access: non-zero-wait-state, direct access, write only address: h664 bit [31:0] content of flow control frame [63:32] 18.2.10.4 afcr - flow control register access: non-zero-wait-state, direct access, write/read address: h670 bit [9:0] reserved bit [12:10] xon_thddefines the minimum # of free fram e buffers before transmitting xon flow control frame. bit [13] queue aging enable tx queue aging function enable bit [14] flush enable when stack is full, enable flush procession 0 = disable 1 = enable bit [15] xon enable full duplex xon enable 0 = disable 1 = enable bit [31:16] reserved 0 content of input flow control frame[31:0] 31 0 content of input flow control frame[63:32] 31 0 31 16 15 14 13 12 ** xn 10 9 f e ae xon_th d **
mds213 data sheet 89 zarlink semiconductor inc. 18.2.10.5 amar[1:0] - multicast address reg. for mac control frames this 6-byte mac address is st ored in two 32-bit registers ? amar0 mac address byte [3:0] ? address: h674 ? amar1 mac address byte [5:4] ? address: h678 access: non-zero-wait-state, direct access, write/read 18.2.10.6 amct - mac control frame type code register access: non-zero-wait-state, direct access, write/read address: h67c ? 2-byte mac control frame type code defined by ieee 802.3x full duplex flow control standard 18.2.10.7 adar [1:0] - base mac address registers the 6-byte mac address is st ored in two 32-bit registers ? adar0 mac address byte [3:0] ? address: h600 ? adar1 mac address byte [5:4] ? address: h604 access: non-zero-wait-state, direct access, write/read ? these two registers define the base mac address of the device. ? bit [3:0] of byte 0 (mac5) is always set to 0. ? mac address for each port is defined by ? mac address for port n = base mac address + mac offset [n] where n = {0..12} ? mac offset[n] is defined by the following registers 0 31 16 15 24 23 mac 5 mac 2 mac 1 mac 3 mac 0 mac 4 8 7 amar0 amar1 0 frame type 31 16 15 8 7 24 23 0 31 16 15 24 23 mac 5 0 0 0 0 mac 2 mac 1 mac 3 mac 0 mac 4 8 7 amar0 amar1 11 3
mds213 data sheet 90 zarlink semiconductor inc. 18.2.10.8 adaor0 - mac offset address register 0 mac offset address for port [7:0], 4-bit per port access: non-zero-wait-state, direct access, write/read address: h608 bit [3:0] mac offset address for port 0 bit [7:4] mac offset address for port 1 bit [11:8] mac offset address for port 2 bit [15:12] mac offset address for port 3 bit [19:16] mac offset address for port 4 bit [23:20] mac offset address for port 5 bit [27:24] mac offset address for port 6 bit [31:28] mac offset address for port 7 usage: there are three ways to assign the mac address to each port. all ports in the same device share the 44 msbs, mac[47:4] in adar[0:1], while the 4 lsbs, mac offset [3:0] can be assigned as follows: 1. in a managed system, if the device does not support po rt trunking, mac_offset[3:0]= the port number. 2. in a managed system where device supports port trunking, the ports in the same trunk group shares the same mac[3:0]. the value of mac[3:0] is assigned by the smallest port number in the trunk group. 3. in a managed system, if bit [18] of dcr2, smac=0, all ports are assigned to a single mac. 4. in an unmanaged system, mac[3:0] is fixed for all dev ices (i.e., only one mac[3:0] address for the whole system). 18.2.10.9 adaor1 - mac offset address register 1 mac offset address for po rt [12:8], 4-bit per port access: non-zero-wait-state, direct access, write/read address: h60c bit [3:0] mac offset address for port 8 bit [7:4] mac offset address for port 9 bit [11:8] mac offset address for port 10 bit [15:12] mac offset address for port 11 bit [19:16] mac offset address for port 12 bit [31:20] reserved 24 23 port7_offset 31 28 27 20 19 12 11 8 7 4 3 0 port6_offset port5_offset port4_offset port3_offset port2_offset port1_offset port0_offset 16 15 31 20 19 12 11 8 7 4 3 0 port12_offset port11_offset port10_offset port9_offset port8_offset 16 15
mds213 data sheet 91 zarlink semiconductor inc. 18.2.10.10 acktm - timer for sof checking access: non-zero-wait-state, direct access, write/read address: h610 bit [9:0] xoff_cktm the time out value to check sof after xoff bit [31:10] reserved note that the purpose of this timer is to avoid continuously sending the xo ff frames. the xoff frame is triggered by the incoming frames when no resources are available in the ds chip. ideally, after the first xoff frame is sent out, we expect no frames to be received until we send out the xon frame. however, the connected device may not interpret xoff frames correctly (or may react slowly) and still keep sending data frames to this congested port. in this case, the congested port will want to send another xoff frame each time another frame is received. to avoid this scenario, we set the acktm timer to prevent the conges ted port from sending xoff frames for every incoming frame in congestion period before the timer expires. 18.2.10.11 afcht10 - flow control hold time of 10mbps port access: non-zero-wait-state, direct access, write/read address: h620 bit [15:0] hbk_tm_10 holding time to remote station for 10 mbps port when the chip detects the head of line blocking counter has run out. the holding time value is embedded in the flow control frame sent to the remote station. bit [31:16] reserved 18.2.10.12 afcht 100 - flow control hold time of 100mbps port access: non-zero-wait-state, direct access, write/read address: h624 bit [15:0] hbk_tm_100 holding time to remote station for 100 mbps port when the chip detects the head of line blocking counter has run out. the holding time value is embedded in the flow control frame sent to the remote station. bit [31:16] reserved 31 9 0 xoff_cktm 10 31 16 15 0 hbk_tm_10 31 16 15 0 hbk_tm_100
mds213 data sheet 92 zarlink semiconductor inc. 18.2.10.13 afcht1000 - flow control hold time of giga port access: non-zero-wait-state, direct access, write/read address: h628 bit [15:0] hbk_tm_g holding time to remote station for 1000 mbps port when the chip detects the head of line blocking coun ter has run out. the holding time value is embedded in the flow control frame sent to the remote station. bit [31:16] reserved 18.2.10.14 afcoft10 - flow control off time of 10mbps prot access: non-zero-wait-state, direct access, write/read address: h614 bit [15:0] fl_off_10m off time to the remote station for 10 mbps port when the chip detects the buffer resource is not availabl e. the off time value is embedded in the flow control frame sent to the remote station. bit [31:16] reserved 18.2.10.15 afcoft100 - flow control off time of 100mbps port access: non-zero-wait-state, direct access, write/read address: h618 bit [15:0] fl_off_100m off time to remote station for 100 mbps port when the chip detects the buffer resource is not ava ilable. the off time value is embedded in the flow control frame sent to the remote station. bit [31:16] reserved 31 16 15 0 hbk_tm_g 31 16 15 0 fl_off_10m 24 23 31 16 15 0 fl_off_100m 24 23
mds213 data sheet 93 zarlink semiconductor inc. 18.2.10.16 afcoft1000 - flow control off time of giga port access: non-zero-wait-state, direct access, write/read address: h61c bit [15:0] fl_off_g off time to remote statio n for 1000 mbps port when the chip detects the buffer resource is not ava ilable. the off time value is embedded in the flow control frame sent to the remote station. bit [31:16] reserved 18.2.11 access control function group 2 (chip level) 18.2.11.1 apmr- port mirroring register access: non-zero-wait-state, direct access, write/read address: h5c0 bit [11:0] mirr_port the 10/100 port chosen to be mirrored bit [12] local/remote indicates the mirrored port is from a local or remote device. 0=local 1=remote ( note not support 1g port mirroring.) bit [13] rx/tx indicates whether the mirror is receiving data or transmitting data bit [14] mp0 mirror to port 0 (default=0) mp0=1 mirror to port 0 mp0=0 mirror not go to port 0 bit [31:15] reserved 18.2.11.2 pfr - protocol filtering register access: non-zero-wait-state, direct access, write/read address: h5c4 the search engine will provide ingress filtering on a per-devis e basis. each bit of pf regi ster (default value = 0) will cause packets matching that category to be dropped. 31 16 15 0 fl_off_g 24 23 0 31 mirror port mp rx/ tx l/r 0 15 14 13 12 11 0 31 16 15 3 8 7 6 5 4 1 2
mds213 data sheet 94 zarlink semiconductor inc. bit [7:0] protocol filter for unicast frames bit [0] ip - ethernet ii encapsulation bit [1] ip - 802_snap encapsulation bit [2] ipx - ethernet ii encapsulation bit [3] ipx - 802_snap encapsulation bit [4] ipx - 802.2 encapsulation bit [5] ipx - 802.3_raw encapsulation bit [6] other (packets with unknown enc apsulation, or non-ip, non-ipx packets) bit [7] untagged frames bit [15:8] protocol filter for multicast frames bit [8] multicast ip - ethernet ii encapsulation bit [9] multicast ip - 802_snap encapsulation bit [10] multicast ipx - ethernet ii encapsulation bit [11] multicast ipx - 802_snap encapsulation bit [12] multicast ipx - 802.2 encapsulation bit [13] multicast ipx - 802.3_raw encapsulation bit [14] multicast other (packets with unknow n encapsulation, or non-ip, non-ipx packets) bit [15] multicast untagged frames bit [31:16] reserved usage: there is only one pfr register. for each port there is an enable bit(ecr1 bit 6: ife- ingress filter enable) which determines whether the setti ngs in pfr are applied to that port. 18.2.11.3 thkm [0:7] - tr unking forwarding port mask 0-7 eight trunking hash key mask registers shared the same format. ? thkm0 trunking forwarding port mask 0 forwarding port mask for hash key 0 address:h5c8 ? thkm1 trunking forwarding port mask 1 forwarding port mask for hash key 1 address:h5cc ? thkm2 trunking forwarding port mask 2 forwarding port mask for hash key 2 address:h5d0 ? thkm3 trunking forwarding port mask 3 forwarding port mask for hash key 3 address:h5d4 ? thkm4 trunking forwarding port mask 4 forwarding port mask for hash key 4 address:h5d8 ? thkm5 trunking forwarding port mask 5 forwarding port mask for hash key 5
mds213 data sheet 95 zarlink semiconductor inc. address:h5dc ? thkm6 trunking forwarding port mask 6 forwarding port mask for hash key 6 address:h5e0 ? thkm7 trunking forwarding port mask 7 forwarding port mask for hash key 7 address:h5e4 access:non-zero-wait-state,direct access,write/read bit [11:0] tk_mskport trunk mask for trunking hash key bit [31:12] reserved cpu sets up this table as follows: 1. set all bits not in trunk groups to 1 2. set all bits in the trunk group to 0 3. pick one forwarding port per trunk group and turn t he corresponding bit to 1 (each hash key may have different forwarding ports, the rule to pick forwarding ports is up to the cpu). usage: these masks are used to prevent flooded or multicas t packets from being transmitted out with more than one port on a trunk. the trunking hash key is used to se lect the proper mask (for load distribution). the mask value will be set up to mask off all but one port within each trunk group. 18.2.11.4 ipmcas - ip multicast mac address signature usage: for following four regi sters ipmcas0, ipmcas1, ipmcmsk0 and ipmcmsk1, are used to distinguish between ip multicast traffic and regular multicast. the mac for ip multicast are h"01:00:5e:00:00:00" to h" 01:00:5e:7f:ff:ff" and the mask for ipmc is: h"ff:ff:ff:80:00:00". the 6-byte of ip multicast mac addr ess is stored in tw o 32-bit registers ? ipmcas0 ip multicast mac address byte [3:0] address:h5e8 ? ipmcas1 ip multicast mac address byte [5:4] address:h5ec access:non-zero-wait-state,direct access,write/read ? these two registers define the mac address signature of ip multicast. ? default = h" 01:00:5e:7f:ff:ff" 31 11 0 tk_msk 12 0 mac 5 mac 2 mac 1 mac 3 mac 0 mac 4 11 ipmcas0 ipmcas1 8 7 16 15 24 23 31
mds213 data sheet 96 zarlink semiconductor inc. 18.2.11.5 ipmcmsk- ip multicast mac address mask the 6-byte of ip multicast mac mask is stored in two 32-bit registers ? ipmcas0 ip multicast mac mask byte [3:0] address:h5f0 ? ipmcas1 ip multicast mac mask byte [5:4] address:h5f4 access:non-zero-wait-state,direct access,write/read these two registers define the mac mask of ip multicast. default = h"ff:ff:ff:80:00:00". 18.2.11.6 cfcbhdl - fcb handle register for cpu read access: non-zero-wait-state, direct access, read only address: h580 usage: when cpu requests a free fdb to writ e a frame, it must request a free fcb via this register. the register contains a free handle of fcb, which also pointer to a free fdb. cpu reads fcb handle: (when the cpu writ e fdb, it requires a fdb handle first). cpu checks cfcbhdl[31],h_rdy ready or not. if so, cpu gets the fcb handle from cfcbhdl[9:0] bit [9:0] fcb_handle fcb handle address bit [30:10] reserved bit [31] h_rdy fcb handle ready 0=not ready 1=ready 18.2.11.7 cpu access internal rams (tables) usage: (refer to section 9 for detail). the cpu uses the following methods to access the fi ve internal rams, including mcid, vlan port mapping (vmap), bm control table (bmct), fcb and transmission queue control (qcnt). registers: ? cpuircmd : command register ? cpuirdat0 : data register for specific entry of content bit[31:0] ? cpuirdat1 : data register for specific entry of content bit[63:32] ? cpuirdat2 : data register for specific entry of content bit[95 64] ? cpuirrdy : data read ready. 0 mask 5 mask 2 mask 1 mask 3 mask 0 mask 4 11 ipmcmsk0 ipmcmsk1 8 7 16 15 24 23 31 31 10 9 0 fcb_handle[9:0] h_r dy
mds213 data sheet 97 zarlink semiconductor inc. cpu reads fcb ? cpu write the read command into cpuircmd with fcb handle, w/r=0. and set c_rdy. also, set the table type = fcb, (cpuircmd[14]=1) ? frame engine puts the specified fcb content into cpuirdatl and cpuirdatm ? frame engine clear c_rdy ? frame engine set cpuirrdy[0] to notify cpu that the fcb data is ready to be read. cpu writes fcb ? cpu writes the content of fcb into cpuirdatl and cpuirdatm ? cpu writes the handle of fcb into cpuircmd [9:0], set cpuircmd [10] = 1,(write cmd), set cpuircmd[31]=1, cmd_rdy and set the table index to fcb, (cpuircmd[14]=1). ? frame engine clears cpuircmd [31], c_rdy, when frame engine reads fcb done ? apply the similar method to access the other four tables. 18.2.11.8 cpuircmd - cp u internal ram command register access: non-zero-wait-state, direct access, write/read address: h584 command for cpu accesses five internal tables bit [9:0] entry index the index of specified entry type = mcid(16) entry index[3:0] type = vmap(256) entry index[7:0] type = bmct(1k) entry index[9:0] type = fcb(1k) entry index[9:0] type = qcnt (64) entry index[5:0] bit [10] w/r write or read the table entry 0=read 1=write bit[15:11] table bit map bit maps of five tables. bit[11] mcid mcid=1 use mc id l table bit[12] vmap vmap=1 use vlan port mapping table (vmap) bit[13] bmct bmct=1 use buffer manager control table (bm control) bit[14] fcb fcb=1 use fcb table bit[15] qcnt qcnt=1 use transmission queue control table (qm control) bit [30:16] reserve bit [31] c_rdy command ready 0=not ready 1=ready 0 30 16 15 14 13 12 11 10 9 entry index [9:0] qc fc b bm nt c_r dy ct vm ap mc id w/ r 31
mds213 data sheet 98 zarlink semiconductor inc. 18.2.11.9 cpuirdat - cpu internal ram data register the 3 data registers are used when cpu reads or wr ites the content of the specified entry. table ? cpuirdat0 cpu internal ram data register for data[31:0] address: h588 ? cpuirdat1 cpu internal ram data register for data[63:32] address: h58c ? cpuirdat2 cpu internal ram data register for data[95:64] address: h590 access: non-zero-wait-state, direct access, write/read the content is dependent as to the ty pe of table, as describe follows. type = mc id (6bits) bit [5:0] mcid multicast id fifo data output (note that up to 16 for this version.) bit [31:6] reserved type = vmap table (27 bits) bit [12:0] vlan port enable [12:0] one bit for each ethernet mac port identify the ports associated with each vlan 0 = disable 1 = enable bit [25:13] vlan tag enable [12:0] one bit for each ethernet mac port 0 = disable 1 = enable bit [26] re remote ports enable: indi cate some members in the remote device. 0=disable1=enable bit [31:27] reserved 31 0 data[31:0] data[63:32] data[95:64] cpirdat0 cpirdat1 cpirdat2 31 0 mcid[5:0] cpirdat0 6 5 31 13 12 0 vlan tag enable [12:0] re vlan port en able [12:0] 27 26 25 cpirdat0
mds213 data sheet 99 zarlink semiconductor inc. type = bmct (12bits) bit [11:0] bm buffer management control fifo output bm stores free fcb handles. (f cb handle=0 cannot be used.) bit [31:12] reserved type = fcb (56 bits) bit [55:0] fcb frame control block. refer to chapter 9 for detailed data structure. type = qcnt (79 bits) bit [2:0] que_s [2:0] queue size 000=128 entries 001=128*2 entries 111=128*8=1k entries each entry contains 4 bytes bit [14:3] base [11:0] base pointer to its transmission queue bit [25:15] ecnt [10:0] entry count: total entries in its queue. bit [35:26] wrpt [9:0] write pointer address_write_entry[20:9]=base[11:0]+wrpt[9:7] address_write_entry[9:3]= wrpt[6:0] address_write_entry[2:0]= 0 (the address [2:0] is always equal to 0.) bit [45:36] rdpt [9:0] read pointer address_read_entry[20:9] =base[11:0]+rdpt[9:7] address_read_entry[9:3]= rdpt[6:0] address_read_entry[2:0]= 0 (the address [2:0] is always equal to 0.) bit[46] cv cache valid cv=1, cache of queue entry qe[31:0] is valid. bit[78:47] qe[31:0] cache a queue entry 31 bm[11:0] 12 11 cpuirdat0 0 31 0 fcb_data[31:0] 24 23 fcb_data[55:32] cpuirdat0 cpuirdat1 31 0 base[11:0] 15 14 13 wrpt[5:0] cpuirdat0 cpuirdat1 qs[2:0] wrpt[9:6] rdpt[9:0] cache queue entry[31:17] ecnt[10:0] cv cache queue entry[16:0] 4 3 2 cpuirdat2
mds213 data sheet 100 zarlink semiconductor inc. 18.2.11.10 cpuirrdy - inte rnal ram read ready for cpu access: non-zero-wait-state, direct access, write/read address: h594 the frame engine sets this ready bit to notify t he cpu that the requested da ta is ready to read. bit [0] r_rdy data in data registers is ready for cpu read bit [31:1] reserved 18.2.11.11 ledr- led register access: non-zero-wait-state, direct access, write/read address: h598 bit [7:0] udef1 user defined information status 1 for debug purpose bit [15:8] udef2 user defined information status 2 for debug purpose bit [23:16] udef3 user defined information status 3 for debug purpose bit [25:24] ht holding time for led signal (default=00) 00=8msec 01=16msec 10=32msec 11=64msec bit [27:26] lclk led clock frequency (default=00) 00= 100m/8=12.5mhz 01= 100m/16=6.25mhz 10= 100m/32=3.125mhz 11= 100m/64-1.5625mhz bit [30:28] reserve bit [31] ss start shift the status bi ts out from the master device. this bit has no effect on the slave chip. note: udef1-udef3 are used for debug purpose. the conten ts of udef1-3 are loaded by cpu and the usage of these are up to software. 18.2.12 ethernet mac port control registers one set for each ethernet mac port [12:0] mii related controls applies to port [1:0] only port 12 is always dedicated to gmac 31 1 0 rd y 31 30 0 ht ss 28 27 26 25 24 23 16 15 8 7 lck udef3 udef2 udef1
mds213 data sheet 101 zarlink semiconductor inc. 18.2.12.1 ecr0 - ecr0 - mac port control register access: non-zero-wait-state, direct access, write/read address: h0x0*4 x: port n h000 ecr0_p0 h040 ecr0_p1 h080 ecr0_p2 h0c0 ecr0_p3 h100 ecr0_p4 h140 ecr0_p5 h180 ecr0_p6 h1c0 ecr0_p7 h200 ecr0_p8 h240 ecr0_p9 h280 ecr0_p10 h2c0 ecr0_p11 h300 ecr0_p12 bit [0] rr reset receiver bit [1] xr reset transmitter bit [2] re rx enable bit [3] rp rst_pcs, reset pcs logic ( only apply gigabit port ) port is disabled when both rr & xr bits are set. 18.2.12.2 ecr1 - mac port configuration register access: non-zero-wait-state, direct access, write/read address: h0x1*4x: port number h004 ecr1_p0 h044 ecr1_p1 h084 ecr1_p2 h0c4 ecr1_p3 h104 ecr1_p4 h144 ecr1_p5 31 3 2 1 0 r rp re r x r
mds213 data sheet 102 zarlink semiconductor inc. h184 ecr1_p6 h1c4 ecr1_p7 h204 ecr1_p8 h244 ecr1_p9 h284 ecr1_p10 h2c4 ecr1_p11 h304 ecr1_p12 port trunking id bits bit [2:0] tgid group id bit [3] te trunk enable 0= trunk disable 1= trunk enable unicast blocking control bits bit [5:4] block_uc_frame instructs the rx mac to discard incoming unicast frames. this feature is used by spanning tree. 0x blocking, all frames (default state) 10 learning but not forwarding 11 forwarding all frames bit [6] ife ingress filter enable default = 0 used to enable protocol filtering on a port by port basis. there is only one protocol filtering regist er (pfr), but it can be used on any combination of ports. 0= disable ingress filter 1= enable ingress filter physical layer control bits bit [7] 10m 10m or 100m; 1=10mbps 0=100mbps bit [8] reserved bit [9] full_duplex enables full dupl ex modedefault =0 - half duplex bit [10] fdx_polarity selects the output polarity of full_duplex control signal 0 = low true (default) 1 = high true bit [11] int_lpback setting this bit cause internal connect txclk, txd, txd[0:3] to rxclk, rxd, rxd[0:3] 31 8 7 6 5 4 3 2 0 tg id t 24 23 17 16 15 ife configuration bits trunking e bkuc ifg
mds213 data sheet 103 zarlink semiconductor inc. default =0 - disable bit [12] ext_lpback setting this bit indicate an external loop-back (connection of txclk, txd[0: 3] to rxclk, rxd[0:3] are required) default =0 -- disable bit [13] fc_enable flow control enabledefault =0 - disable when enabled: ?in half duplex mode, the mac transmitter applies back pressure for flow control. ?in full duplex mode, the mac transmitter sends flow-control frames when necessary. the mac receiver interprets and processes incoming flow control frames. the mac receiver marks all flow control frames. receive dma discards the received flow control fram e and send status reports to the switch manager for statistic collection. when disabled: ? the mac transmitter does not asserts flow control by sending flow control frames nor jamming collision. ? the mac receiver still interprets and processes the flow-control frames. the mac receiver marks all flow control frames. receive dma discards the received flow control frames and send a status report to the switch manager for statistic collection. bit [14] link_polarity selects the in put polarity of link status signal 0 = low true (default) 1 = high true bit [15] tx_enable enables mac transmitter for transmission default =0 - disable bit [16] reserved bit [23:17] ifg inter-frame gap (default=7'd24) use to adjust the inter-frame gap. (unit =transmit clock.) the default is 7'd24, stands for 24 transmit clock (each clock transmit 4 bits). bit [31:24] reserved 18.2.12.3 ecr2 - mac port interrupt mask register access: non-zero-wait-state, direct access, write/read address: h0x2*4 x: port number h008 ecr2_p0 h048 ecr2_p1 h088 ecr2_p2 h0c8 ecr2_p3 h108 ecr2_p4
mds213 data sheet 104 zarlink semiconductor inc. h148 ecr2_p5 h188 ecr2_p6 h1c8 ecr2_p7 h208 ecr2_p8 h248 ecr2_p9 h288 ecr2_p10 h2c8 ecr2_p11 h308 ecr2_p12 bit [0] was if set, the status counter wrap around signal is masked. bit [1] link_change if set, the link_up and link_down interrupts are masked. bit [31:2] reserved link change interrupts are automatically disabled whenever both mac transmitter & receiver are in reset state - i.e. both xr & rr bits are set. 18.2.12.4 ecr3 - mac port interrupt status register access: non-zero-wait-state, direct access, read only address:h0x3*4 x: port number h00c ecr3_p0 h04c ecr3_p1 h08c ecr3_p2 h0cc ecr3_p3 h10c ecr3_p4 h14c ecr3_p5 h18c ecr3_p6 h1cc ecr3_p7 h20c ecr3_p8 h24c ecr3_p9 h28c ecr3_p10 h2cc ecr3_p11 h30c ecr3_p12 31 2 1 0 mask
mds213 data sheet 105 zarlink semiconductor inc. bit [0] was wrapped around signal. bit [1] link_change this bit is set wh en the mac determines that the status of physical link has been changed bit [2] lk_up 0=link down, 1=link up this bit is reset whenever the phy has identified the lost of physical link integrity. bit [31:3] reserved 18.2.12.5 ecr4 - port status counter wrapped signal access: non-zero-wait-state, direct access, read only address: h0x4*4 x: port number h010 ecr4_p0 h050 ecr4_p1 h090 ecr4_p2 h0d0 ecr4_p3 h110 ecr4_p4 h150 ecr4_p5 h190 ecr4_p6 h1d0 ecr4_p7 h210 ecr4_p8 h250 ecr4_p9 h290 ecr4_p10 h2d0 ecr4_p11 h310 ecr4_p12 b[0]. 0-d bytes sent(d) b[1]. 1-l unicast frames sent b[2]. 1-u flow control sent 31 3 2 1 0 status 31 30 0 status wrapped signal
mds213 data sheet 106 zarlink semiconductor inc. b[3]. 2-l non-unicast frame sent b[4]. 2-u1 frame send fail b[5]. 2-u2 alignment error b[6]. 3-d bytes received (good or bad) (d) b[7]. 4-d frames received (good or bad) (d) b[8]. 5-d total bytes received (good) (d) b[9]. 6-l total frames received (good) b[10]. 6-u flow control frames received b[11]. 7-l multicast frames received b[12]. 7-u broadcast frames received b[13]. 8-l frames with length of 64 bytes b[14]. 8-u jabber frames b[15]. 9-l frames with length between 65-127 bytes b[16]. 9-u oversize frames b[17]. a-l frames with length between 128-255 bytes b[18]. a-u frames with length between 256-511 bytes b[19]. b-l frames with length between 512-1023 bytes b[20]. b-u frames with length between 1024-1528 bytes b[21]. c-l undersize frames b[22]. c-u fragment b[23]. d-l crc b[24]. d-u short event b[25]. e-l collision b[26]. e-u drop b[27]. f-l filtering counter b[28]. f-u1 delay exceed discard counter b[29]. f-u2 late collision note: each port owns a counter block, containing 16 doubl e words. the 29 bits indica te that each corresponding counter is wrapping around the signal. the type and location of each counter is specified by the following format. the format description : x-y: x means the relative physical address in its counter blocks. : y indicates the type of counter it is (notation "c"= double word read from ram block) d: c[31:0] double word counter
mds213 data sheet 107 zarlink semiconductor inc. l: c[23:0] 24 bits counter u: c[31:24] 8 bits counter u1: c[23:16] 8 bits counter u2: c[31:24] bits counter (the same as notation "u") l: c[15:0] 16 bits counter u c[31:16] 16 bits counter 18.2.12.6 pvid register access: non-zero-wait-state, direct access, write/read address: h0x9*4 x: port number for default vlan id h024 pvidr_p0 h064 pvidr _p1 h0a4 pvidr _p2 h0e4 pvidr _p3 h124 pvidr _p4 h164 pvidr _p5 h1a4 pvidr _p6 h1e4 pvidr _p7 h224 pvidr _p8 h264 pvidr _p9 h2a4 pvidr _p10 h2e4 pvidr _p11 h324 pvidr _p12 bit [0:11] port vlan id (pvid) bit [12] reserved bit [15:13] priority bit [31:16] reserved 31 0 port vlan id 16 15 13 12 11 priority
mds213 data sheet 108 zarlink semiconductor inc. 19.0 dc electrical characteristics 19.1 absolute maximum ratings package: 456 hbga (heatslug bga) storage temperature: -65c to +150c operating temperature: 0c to +70c maximum junction temperature:125c supply voltage vcc with respect to vss +3.0 v to +3.6 v supply voltage vdd with respect to vss +2.38 v to +2.75 v voltage on 5v tolerant input pins -0.5 v to (vcc + 3.3 v) caution : stresses above those listed may cause permanent device failure. functionality at or above these limits is not implied. exposure to the abso lute maximum ratings for extended per iods may affect device reliability. 19.2 dc electrical characteristics vcc = 3.0 v to 3.6 v (3.3v +/- 10%)t ambient = 0 c to +70 c vdd = 2.5v +10% - 5% note 1: when external heat sink is attached, ja is reduced by about 8-12% in still air. recommended operating conditions symbol parameter description min. type max. unit f osc frequency of operation 100 mhz i cc supply current - @ 100 mhz (vcc =3.3 v) 270 351 ma i dd supply current - @ 100 mhz (vdd =2.5 v) 780 1014 ma v oh output high voltage (cmos) 2.4 v v ol output low voltage (cmos) 0.4 v v ih-ttl input high voltage (ttl 5v tolerant) 2.0 vcc + 2.0 v v il-ttl input low voltage (ttl 5v tolerant) 0.8 v i il input leakage current (all pins except those with internal pull-u p/pull-down resistors) 10 a i ol output leakage current 10 a c in input capacitance 5 pf c out output capacitance 5 pf c i/o i/o capacitance 7 pf ja thermal resistance with 0 air flow 12 1 c/w ja thermal resistance with 1 m/s air flow 11 c/w ja thermal resistance with 2 m/s air flow 9.6 c/w jc thermal resistance between junction and case 3.3 c/w
mds213 data sheet 109 zarlink semiconductor inc. 20.0 ac specifications 20.1 xpipe interface figure 26 - xpipe interface - output valid delay timing x1-max x1-min x4-max x4-min x3-max x3-min x2-max x2-min x_dclki x_fco x_do[31:0] x_dclko x17 x18 x19 x20 x_di[31:0] x21 x22 x_deni x_fci x_dclki x_deno xpipe interface - output valid delay timing xpipe interface - input setup and hold timing x16 s_clk x15 x_dclk
mds213 data sheet 110 zarlink semiconductor inc. symbol parameter -100 mhz note min (ns) max (ns) x1 x_dclko output valid delay 1 5 c l = 30pf x2 x_do[31:0] output valid delay 1 5 c l = 30pf x3 x_deno output valid delay 1 5 c l = 30pf x4 x_fco output valid delay 1 5 c l = 30pf x15 x_dclki input set-up time 3 reference s-clk x16 x_dclki input hold time 0 reference s-clk x17 x_di[31:0] input set-up time 3 x18 x_di[31:0] input hold time 0 x19 x_deni input set-up time 3 x20 x_deni input hold time 0 x21 x_fci input set-up time 3 x22 x_fci input hold time 0 table 11 - ac characteristics - xpipe interface
mds213 data sheet 111 zarlink semiconductor inc. 20.2 cpu bus interface figure 27 - ac characteristics - cpu bus interface p19-max p19-min p23-max p23-min p24-max p24-min p_clk p_rdy# p_d[31:0] p_int cpu bus interface - output valid delay timing p1 p2 p3 p4 p_rst# p5 p6 p_ads# p7 p8 p_rwc# p_clk cpu bus interface - input setup and hold timing p9 p10 p11 p12 p_a[10:1] p_csi# p_d[31:0] p15 p16 p17 p18 p_reqc p_req1 p20-max p20-min p21-max p21-min p22-max p22-min p_rwc# p_a[10:1] p_ads# p25-max p25-min p26-max p26-min p_gnt1 p_gntc
mds213 data sheet 112 zarlink semiconductor inc. symbol parameter -66 mhz note min (ns) max (ns) p_clk p1 p_rst# input setup time 6 p2 p_rst# input hold time 2 p3 p_ads# input setup time 6 p4 p_ads# input hold time 2 p5 p_rwc# input setup time 6 p6 p_rwc# input hold time 2 p7 p_csi# input setup time 6 p8 p_csi# input hold time 2 p9 p_a[10:1] input setup time 6 p10 p_a[10:1] input hold time 2 p11 p_d[31:0] input setup time 6 p12 p_d[31:0] input hold time 2 p15 p_reqc input setup time 6 p16 p_reqc input hold time 2 p17 p_reqi input setup time 6 p18 p_reqi input hold time 2 p19 p_d[31:0] output valid delay 2 12 c l = 65pf p20 p_a[10:1] output valid delay 2 9 c l = 50pf p21 p_rwc# output valid delay 2 9 c l = 50pf p22 p_ads# output valid delay 2 9 c l = 50pf p23 p_rdy# output valid delay 2 9 c l = 50pf p24 p_int output valid delay 2 9 c l = 30pf p25 p_gntc output valid delay 2 9 c l = 20pf p26 p_gnt1 output valid delay 2 9 c l = 20pf table 12 - ac characteristics - cpu bus interface
mds213 data sheet 113 zarlink semiconductor inc. 20.3 local sbram memory interface figure 28 - local memory interface - input setup and output valid delay timing table 13 - ac characteristics - local sbram memory interface symbol parameter -100mhz note min (ns) max (ns) l_clk c l = 50pf l1 l_d[63:0] input set-up time 3 l2 l_d[63:0] input hold time 1.5 l3 l_d[63:0] output valid delay 2 7 c l = 30pf l4 l_a[20:3] output valid delay 2 7 c l = 50pf l6 l_adsc# output valid delay 2 7 c l = 50pf l7 l_bw[7:0]# output valid delay 2 7 c l = 30pf l8 l_we[1:0]# output valid delay 2 7 c l = 30pf l9 l_oe[1:0]# output valid delay 0 1 c l = 30pf l3-max l3-min l4-max l4-min l6-max l6-min l7-max l7-min l_clk l_a[20:3] l_bw[7:0]# l_d[63:0] l_adsc# local memory interface - l8-max l8-min l_we[1:0]# l9-max l9-min l_oe[1:0]# output valid delay timing l1 l2 l_d[63:0] l_clk local sbram memory interface local memory interface - input setup and hold timing
mds213 data sheet 114 zarlink semiconductor inc. figure 29 - port mirroring interface - input setup and hold timing figure 30 - port mirroring interface - output delay timing figure 31 - reduce media independent interface - input setup and hold timing figure 32 - reduce media independent interface - output delay timing pm_deni m_clk pm_d[1:0] pm1 pm2 pm3 pm4 pm5 pm6-max pm6-min pm7-max pm7-min m_clki pm_deno pm_do[1:0] m[11:0]_rxd[1:0] m_clki m[11:0]_crs_dv m1 m2 m3 m4 m5 m6-max m6-min m7-max m7-min m_clki m[11:0]_txen m[11:0]_txd[1:0]
mds213 data sheet 115 zarlink semiconductor inc. table 14 - ac characteristics - port mirroring interface table 15 - ac characteristics - reduced media independent interface symbol parameter -50 mhz note min (ns) max (ns) pm1 m_clki reference input clock pm2 pm_deni input setup time 1.5 pm3 pm_deni input hold time 2 pm4 pm_di[1:0] input setup time 1.5 pm5 pm_di[1:0] input hold time 2 pm6 pm_deno output delay time 2 11 c l = 30pf pm7 pm_do[1:0] output delay time 2 11 c l = 30pf symbol parameter -50 mhz note min (ns) max (ns) m1 m_clki reference input clock m2 m[11:0]_rxd[1:0] input setup time 1.5 m3 m[11:0]_rxd[1:0] input hold time 2 m4 m[11:0]_crs_dv input setup time 2 m5 m[11:0]_crs_dv input hold time 1 m6 m[11:0]_txen output delay time 2 11 c l = 30pf m7 m[11:0]_txd[1:0] output delay time 2 11 c l = 30pf
mds213 data sheet 116 zarlink semiconductor inc. table 16 - ac characteristics - gigabit media independent interface symbol parameter -125 mhz note min (ns) max (ns) m[12]_rxclk input reference clock g1 m[12]_rxd[7:0] input setup times 2 g2 m[12]_rxd[7:0] input hold times 0 g3 m[12]_rx_dv input setup times 2 g4 m[12]_rx_dv input hold times 0 g5 m[12]_rx_er input setup times 2 g6 m[12]_rx_er input hold times 0 g7 m[12]_crs input setup times 2 g8 m[12]_crs input hold times 0 g9 m[12]_col input setup times 2 g10 m[12]_col input hold times 0 m[12]_txclk output reference clock g11 m[12]_txd[7:0] output delay times 1 5 c l = 20pf g12 m[12]_tx_en output delay times 1 5 c l = 20pf g13 m[12]_tx_er output delay times 1 5 c l = 20pf g 1 g 3 g 5 g 7 g 9 g 2 g 4 g 6 g 8 g 10 m [12]_r x c l k m [ 12] _r x d [7:0 ] m [12]_r x _d v m [12]_r x _e r m [12]_c r s m [ 12] _c o l g 11-m in g 11-m ax g 12-m in g 12-m ax g 13-m in g 13-m ax m [ 12] _tx c l k m [ 12] _tx d [7:0 ] m [ 12] _tx _e n m [ 12] _tx _e r input setup and hold timing output valid delay timing
mds213 data sheet 117 zarlink semiconductor inc. figure 33 - input setup and hold timing figure 34 - output valid delay timing table 17 - ac characteristics - physical media attachment interface figure 35 - led interface - output delay timing symbol parameter -125 mhz note min (ns) max (ns) gp_rxclk0/ gp_rxclk1 input reference clock gp1 gp_rxd[9:0] input setup times 2 gp2 gp_rxd[9:0] input hold times 0 gp_txclk output reference clock gp3 gp_txd[9:0] output delay times 1 5 c l = 20pf gp1 gp2 gp_rxclk0 /gp_rxclk1 gp_rxd[9:0] gp3-min gp3-ma x gp_txclk gp_txd[9:0] le2-max le2-min le3-max le3-min led_clko led_do led_synco le1
mds213 data sheet 118 zarlink semiconductor inc. table 18 - ac characteristics - led interface symbol parameter variable freq. note min (ns) max (ns) le1 le_clko reference output clock le2 le-do output valid delay -1 7 c l = 30pf le3 le_synco output valid delay -1 7 c l = 30pf
c zarlink semiconductor 2003 all rights reserved. apprd. issue date acn package code previous package codes: dimension conforms to jedec ms - 034 e b e e1 a2 d d1 a a1 35.20 34.80 30.00 ref 456 1.27 0.60 0.90 30.00 ref 1.17 ref 34.80 min 0.50 2.20 35.20 2.46 0.70 max 6. substrate thickness is 0.56 mm 4. n is the number of solder balls are defined by the spherical crowns of the solder balls. 2. dimension "b" is measured at the maximum solder ball diameter 1. controlling dimensions are in mm 3. primary datum -c- and seating plane 5. not to scale. d e d1 e1 e a1 a a2
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